From patchwork Fri Sep 14 21:34:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 11434 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EABF123E42 for ; Fri, 14 Sep 2012 21:35:38 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id E54F2A39291 for ; Fri, 14 Sep 2012 21:35:33 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id j25so3512549iaf.11 for ; Fri, 14 Sep 2012 14:35:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-provags-id:x-gm-message-state; bh=j/x6TOndbJeeZFwWy0yp8n54Tsg9Axl/Yyh89RZ3OhI=; b=NxD2hBM9H/gDuQ4q+RFuS69gRXSkI06OL3OnOlwUOBzHbiYts8kmvfapq5IiLuWVWF Ln+HkMLQBH5XTJ5tkcZKE6kgHKUgNNoGXUxzxtJDqrd7UpMb+nXj4w2fbE5agKeTcCeG MAzytFkd2kJLjRBHOdc/GFhSU7RkZuUJfIZd60hSH4tCMOT/gHfM2SjO/z5UfpUaTcTF bFy/T82Fpwh9IIpFot3oevZlFZSUrdvsVwXrrE/ejzJfcV3J/N59697yhqRJ29wsDvfa kVCDP15jFyQP7OH/scz/++hjlcvTzhOCLZBWWCm8QXcnhMzftSxdTKN+ySpC8R0BWvxO wUsg== Received: by 10.50.217.227 with SMTP id pb3mr120937igc.28.1347658533692; Fri, 14 Sep 2012 14:35:33 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp215418igc; Fri, 14 Sep 2012 14:35:32 -0700 (PDT) Received: by 10.204.129.4 with SMTP id m4mr2148269bks.55.1347658532102; Fri, 14 Sep 2012 14:35:32 -0700 (PDT) Received: from moutng.kundenserver.de (moutng.kundenserver.de. [212.227.17.8]) by mx.google.com with ESMTP id hk8si4080514bkc.55.2012.09.14.14.35.31; Fri, 14 Sep 2012 14:35:32 -0700 (PDT) Received-SPF: neutral (google.com: 212.227.17.8 is neither permitted nor denied by best guess record for domain of arnd@arndb.de) client-ip=212.227.17.8; Authentication-Results: mx.google.com; spf=neutral (google.com: 212.227.17.8 is neither permitted nor denied by best guess record for domain of arnd@arndb.de) smtp.mail=arnd@arndb.de Received: from localhost.localdomain (HSI-KBW-149-172-5-253.hsi13.kabel-badenwuerttemberg.de [149.172.5.253]) by mrelayeu.kundenserver.de (node=mrbap2) with ESMTP (Nemesis) id 0LfGuG-1TsHxO38qO-00pHrf; Fri, 14 Sep 2012 23:35:27 +0200 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Russell King , Nicolas Pitre , Arnd Bergmann , Tony Lindgren Subject: [PATCH 17/24] ARM: OMAP: use __iomem pointers for MMIO Date: Fri, 14 Sep 2012 23:34:45 +0200 Message-Id: <1347658492-11608-18-git-send-email-arnd@arndb.de> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1347658492-11608-1-git-send-email-arnd@arndb.de> References: <1347658492-11608-1-git-send-email-arnd@arndb.de> X-Provags-ID: V02:K0:QAYxnKFAJA1HkyW+yM3x3japnLJnjTfs0vOv+wN8IC8 WNFGk2BEgK5ZPz6Oj0TtqYxajagiFTVlX2ZKDq/cG3aYiXxDuw JI1buhRCEUY4fuOxmDT25T5uJvEav7GHUrNhHZFzUYj/pcFtAg yM1tLCQ2Iy5Ayuxlc1uc+Yu416cvRZXPDp23TDt8If73EaV2lN wtHSGR0odSp1XT81Fce6ipUdSooATNKR0MkQWslT8AbJyO7OkR BiM0II4SvuztKABSsoWFy+q4hc3kKJsBT0Futew4G6PbCTqcec i4+hThvLkW9DyD98bXR83JcGlAjT4nACj8aSGSHGt+UK11uF0G CjCJxSloW9LhCAKrCgjxtTutS0pYhfwDbg3FEwqywJmBh4h1VX PXXwalismgdpg== X-Gm-Message-State: ALoCoQmC+y2r8YEwCqLwhqd8JfJRUOEFZRqBcOVrvU+B3lYfHunTIYdmrtzmL0nQf6iSuBDofwhJ ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. Cc: Tony Lindgren Signed-off-by: Arnd Bergmann --- arch/arm/plat-omap/include/plat/hardware.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h index ddbde38..2518f6c 100644 --- a/arch/arm/plat-omap/include/plat/hardware.h +++ b/arch/arm/plat-omap/include/plat/hardware.h @@ -56,9 +56,9 @@ * Timers * ---------------------------------------------------------------------------- */ -#define OMAP_MPU_TIMER1_BASE (0xfffec500) -#define OMAP_MPU_TIMER2_BASE (0xfffec600) -#define OMAP_MPU_TIMER3_BASE (0xfffec700) +#define OMAP_MPU_TIMER1_BASE IOMEM(0xfffec500) +#define OMAP_MPU_TIMER2_BASE IOMEM(0xfffec600) +#define OMAP_MPU_TIMER3_BASE IOMEM(0xfffec700) #define MPU_TIMER_FREE (1 << 6) #define MPU_TIMER_CLOCK_ENABLE (1 << 5) #define MPU_TIMER_AR (1 << 1) @@ -69,7 +69,7 @@ * Clocks * ---------------------------------------------------------------------------- */ -#define CLKGEN_REG_BASE (0xfffece00) +#define CLKGEN_REG_BASE IOMEM(0xfffece00) #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) @@ -86,7 +86,7 @@ #define SETARM_IDLE_SHIFT /* DPLL control registers */ -#define DPLL_CTL (0xfffecf00) +#define DPLL_CTL IOMEM(0xfffecf00) /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) @@ -100,7 +100,7 @@ * UPLD * --------------------------------------------------------------------------- */ -#define ULPD_REG_BASE (0xfffe0800) +#define ULPD_REG_BASE IOMEM(0xfffe0800) #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) #define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) @@ -131,7 +131,7 @@ */ /* Watchdog timer within the OMAP3.2 gigacell */ -#define OMAP_MPU_WATCHDOG_BASE (0xfffec800) +#define OMAP_MPU_WATCHDOG_BASE IOMEM(0xfffec800) #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) @@ -149,8 +149,8 @@ * or something similar.. -- PFM. */ -#define OMAP_IH1_BASE 0xfffecb00 -#define OMAP_IH2_BASE 0xfffe0000 +#define OMAP_IH1_BASE IOMEM(0xfffecb00) +#define OMAP_IH2_BASE IOMEM(0xfffe0000) #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)