From patchwork Fri Sep 14 21:34:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 11441 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E618C23E42 for ; Fri, 14 Sep 2012 21:35:49 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 5D9ACA39249 for ; Fri, 14 Sep 2012 21:35:44 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id j25so3512531iaf.11 for ; Fri, 14 Sep 2012 14:35:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-provags-id:x-gm-message-state; bh=b7ZlLAjOfZ/foYOjK6ujyV1Qv2VXymQFMtjuIMJ9ZYk=; b=M3tfwUMgFS48aXEXuzhnJvnRj9VRYdzD8fB5G9+xoxmgvUMoE4QKw64VgE5dQlzUjd MN0u8qxtLqBYISl9Ho2avAi02juePvk5q1shUWwJvCpy40V6tYACeYLHZD3Chphy5pdX WWhmGvErnWa1vdB8lxgSUQNR2S5IC5oKKopnmtOQJfwSt2gYN5yuDxJhJPKBu/eRDQWm GDYsBn6UR0IUj9CX95uaWN9VtRwT7j5cu7r0wx3egRGo5ITuWhTygJq1ukj6uKXj60z2 AXlD8Dq9F2Flkaww9b9PwZFTsXl6BoCE7T9fHbU/uX5HxWvEhdIDTLF9zZyKam9UTeJM +Srw== Received: by 10.50.195.134 with SMTP id ie6mr121544igc.28.1347658544037; Fri, 14 Sep 2012 14:35:44 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp215429igc; Fri, 14 Sep 2012 14:35:43 -0700 (PDT) Received: by 10.180.104.197 with SMTP id gg5mr715133wib.9.1347658542580; Fri, 14 Sep 2012 14:35:42 -0700 (PDT) Received: from moutng.kundenserver.de (moutng.kundenserver.de. [212.227.17.10]) by mx.google.com with ESMTP id m46si3540782wea.138.2012.09.14.14.35.42; Fri, 14 Sep 2012 14:35:42 -0700 (PDT) Received-SPF: neutral (google.com: 212.227.17.10 is neither permitted nor denied by best guess record for domain of arnd@arndb.de) client-ip=212.227.17.10; Authentication-Results: mx.google.com; spf=neutral (google.com: 212.227.17.10 is neither permitted nor denied by best guess record for domain of arnd@arndb.de) smtp.mail=arnd@arndb.de Received: from localhost.localdomain (HSI-KBW-149-172-5-253.hsi13.kabel-badenwuerttemberg.de [149.172.5.253]) by mrelayeu.kundenserver.de (node=mrbap2) with ESMTP (Nemesis) id 0MW8Zl-1T1QDn1TT7-00XtRC; Fri, 14 Sep 2012 23:35:26 +0200 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Russell King , Nicolas Pitre , Arnd Bergmann , Viresh Kumar , Shiraz Hashim , spear-devel@list.st.com Subject: [PATCH 16/24] ARM: spear13xx: use __iomem pointers for MMIO Date: Fri, 14 Sep 2012 23:34:44 +0200 Message-Id: <1347658492-11608-17-git-send-email-arnd@arndb.de> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1347658492-11608-1-git-send-email-arnd@arndb.de> References: <1347658492-11608-1-git-send-email-arnd@arndb.de> X-Provags-ID: V02:K0:zyWPd/FkvYholnQnrR9SckkvLYdiGRCLYTq6gxLK8Pp opSdF+Iqnv4U9kK9o5tsZB5q2bzowIpIEb2xR60y1eos8tNfqr ZaB3mHLLIRMEsmuy8p0D6txXNO4CshFRW0eEacbIRAUPvZCeva EgnWVNhLl9WIst4lj0DG95grQU7odDmdDkRbFJHm/yESv9PQVy c/8yLTaEbH/1205Fj54kfbpS58HgG+alT5O+qNAshuyfyG0Sqz XGJEqtX9QiyDkUB5cocDcNQ2CbddF3xNHgsWIldY9DOZexcxrs L4d74ji/YoTNrAhCP75yGShjW/RUXOTniL7nwJYbu52ge2Qha1 29d+DrILDznJv6a1XloGnUtTNyalH8Kl64Wh3JyPbIE/M3KBdF 4ke2Ulg6GLifg== X-Gm-Message-State: ALoCoQlorfHP/076C3BQI8FleZrGo5Lnx9B7ecqY4QM+FVwnBzD3bI7z/wBCoL+eG40/inEA/RN8 ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. Cc: Viresh Kumar Cc: Shiraz Hashim Cc: spear-devel@list.st.com Signed-off-by: Arnd Bergmann --- arch/arm/mach-spear13xx/include/mach/spear.h | 14 +++++++------- arch/arm/mach-spear13xx/spear13xx.c | 6 +++--- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h index 65f27de..07d90ac 100644 --- a/arch/arm/mach-spear13xx/include/mach/spear.h +++ b/arch/arm/mach-spear13xx/include/mach/spear.h @@ -17,26 +17,26 @@ #include #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE UL(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) #define MCIF_SDHCI_BASE UL(0xB3000000) #define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE UL(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xFE800000) #define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) #define PERIP_GRP1_BASE UL(0xE0000000) -#define VA_PERIP_GRP1_BASE UL(0xFD000000) +#define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) #define UART_BASE UL(0xE0000000) -#define VA_UART_BASE UL(0xFD000000) +#define VA_UART_BASE IOMEM(0xFD000000) #define SSP_BASE UL(0xE0100000) #define MISC_BASE UL(0xE0700000) -#define VA_MISC_BASE IOMEM(UL(0xFD700000)) +#define VA_MISC_BASE IOMEM(0xFD700000) #define A9SM_AND_MPMC_BASE UL(0xEC000000) -#define VA_A9SM_AND_MPMC_BASE UL(0xFC000000) +#define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) /* A9SM peripheral offsets */ #define A9SM_PERIP_BASE UL(0xEC800000) -#define VA_A9SM_PERIP_BASE UL(0xFC800000) +#define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) #define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) #define L2CC_BASE UL(0xED000000) diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c index cf936b1..e106488 100644 --- a/arch/arm/mach-spear13xx/spear13xx.c +++ b/arch/arm/mach-spear13xx/spear13xx.c @@ -114,17 +114,17 @@ void __init spear13xx_l2x0_init(void) */ struct map_desc spear13xx_io_desc[] __initdata = { { - .virtual = VA_PERIP_GRP2_BASE, + .virtual = (unsigned long)VA_PERIP_GRP2_BASE, .pfn = __phys_to_pfn(PERIP_GRP2_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_PERIP_GRP1_BASE, + .virtual = (unsigned long)VA_PERIP_GRP1_BASE, .pfn = __phys_to_pfn(PERIP_GRP1_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_A9SM_AND_MPMC_BASE, + .virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE, .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE), .length = SZ_16M, .type = MT_DEVICE