From patchwork Fri Aug 31 12:21:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 11134 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 68CCE23E02 for ; Fri, 31 Aug 2012 12:22:22 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 4464EA1846B for ; Fri, 31 Aug 2012 12:21:43 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id j25so4631230iaf.11 for ; Fri, 31 Aug 2012 05:22:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:x-gm-message-state; bh=gFPCJuAUW+cDolPLRxXj3PYfHuSycAUmAPRnR7JmWg8=; b=mQKP7P+/3D4I0CsfDx2fUzKLyQhcqWYkoi6aWVvnkngfwNFJfmf82oCfCnX5X9vLei HWYimxBol/yJbzuKxUQSaAWNCL8OzrP23yQ4Qb+TLBoMfm3hil2XrLaLTP9VTD/nJQK8 LaPrAxXtzoaEZreiisFxGmwPWt6jasln+LKr0u2mO/f88+K2pebYpJG2debeHsI0rcYf VKLCfOaIt7Zgq2D4t0dkcrgEu8AKkcYxqOkB8n0L9XJxMgpgiwccR0X4LfRqnhSljQQD NJw2m4oiAcfjnTVQ/aqCkZ0vWZMlLDQA91Hmy0QGAgHifIS2hVPsWEgttCW5jmyJuzTn hstA== Received: by 10.50.7.212 with SMTP id l20mr2429208iga.43.1346415741128; Fri, 31 Aug 2012 05:22:21 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp8432igc; Fri, 31 Aug 2012 05:22:20 -0700 (PDT) Received: by 10.14.179.200 with SMTP id h48mr10921920eem.12.1346415739537; Fri, 31 Aug 2012 05:22:19 -0700 (PDT) Received: from eu1sys200aog115.obsmtp.com (eu1sys200aog115.obsmtp.com [207.126.144.139]) by mx.google.com with SMTP id c41si3199652eem.122.2012.08.31.05.22.11 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 31 Aug 2012 05:22:19 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) client-ip=207.126.144.139; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) smtp.mail=ulf.hansson@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKUECscsaywMOJzfMZv1pr8OvDVAIIUm5A@postini.com; Fri, 31 Aug 2012 12:22:19 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 2A5B549; Fri, 31 Aug 2012 12:21:41 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id B96EC49; Fri, 31 Aug 2012 08:31:58 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 19EB924C2E5; Fri, 31 Aug 2012 14:22:02 +0200 (CEST) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Fri, 31 Aug 2012 14:22:08 +0200 From: Ulf Hansson To: , Mike Turquette , Mike Turquette , Samuel Ortiz , Cc: Linus Walleij , Lee Jones , Philippe Begnic , Srinidhi Kasagar , Ulf Hansson Subject: [PATCH 4/4] clk: ux500: Define smp_twd clock for u8500 Date: Fri, 31 Aug 2012 14:21:31 +0200 Message-ID: <1346415691-13371-5-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com> References: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlAjvy+7IJyIjlJfesiEUg5SYcnEYsdxV/DYVwM8PafuD8s0v35ewDpQ/U+/ZPvk3UU19LY From: Ulf Hansson The smp_twd clock is based upon a prcmu_rate clock type for the PRCMU_ARMSS clock. Signed-off-by: Ulf Hansson --- drivers/clk/ux500/u8500_clk.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 5c1fca1..ca4a25e 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -205,12 +205,16 @@ void u8500_clk_init(void) clk_register_clkdev(clk, "dsilp2", "dsilink.2"); clk_register_clkdev(clk, "dsilp2", "mcde"); + clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS, + CLK_IS_ROOT|CLK_GET_RATE_NOCACHE| + CLK_IGNORE_UNUSED); + clk_register_clkdev(clk, NULL, "smp_twd"); + /* * FIXME: Add special handled PRCMU clocks here: - * 1. smp_twd, use PRCMU_ARMSS. - * 2. clk_arm, use PRCMU_ARMCLK. - * 3. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. - * 4. ab9540_clkout1yuv, see clkout0yuv + * 1. clk_arm, use PRCMU_ARMCLK. + * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. + * 3. ab9540_clkout1yuv, see clkout0yuv */ /* PRCC P-clocks */