From patchwork Fri Aug 31 12:21:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 11132 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 723B723E02 for ; Fri, 31 Aug 2012 12:22:15 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id F3112A1846B for ; Fri, 31 Aug 2012 12:21:36 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id k11so1616760iea.11 for ; Fri, 31 Aug 2012 05:22:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:x-gm-message-state; bh=7F4ggBAdsRhfmkci/UKi4wbXkw/lCRBDxWFfJclyvEw=; b=GRax1vlaNBoichXto28FepxCuJ3IzxQxYOrJa1RYywDQ/4JWLfVAK56RB3VDr0Z37/ +o/e29/HjgCYEyVVj8mSSQjpN0DYmTLAb+lu3VqXyuf+XDcwWCVfJMzkMvUfCEW6k51l GpAATMgnCK1/a7FzlJ8avaksyI56FwYPGjfCT4pbgzTVdi0aBXj8NLBwlDM4SFawzXqA YnyWWwJHGtc7TodaNuPWwGcxf6Cr2PcEvzv1u8J+nsamO9kkY/Z0EAJ2k5H2/nfmZFV3 nhWQ3ifGqzfmaaDsHYlywmykgFzuhzJGAW9iOKZGYiaNN0O6gfKd2xPyhO5PdROp3Cva Urfg== Received: by 10.50.159.196 with SMTP id xe4mr2426924igb.43.1346415734904; Fri, 31 Aug 2012 05:22:14 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp8427igc; Fri, 31 Aug 2012 05:22:14 -0700 (PDT) Received: by 10.14.223.9 with SMTP id u9mr10852808eep.10.1346415733969; Fri, 31 Aug 2012 05:22:13 -0700 (PDT) Received: from eu1sys200aog115.obsmtp.com (eu1sys200aog115.obsmtp.com [207.126.144.139]) by mx.google.com with SMTP id o42si3220912eep.35.2012.08.31.05.22.06 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 31 Aug 2012 05:22:13 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) client-ip=207.126.144.139; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of ulf.hansson@stericsson.com) smtp.mail=ulf.hansson@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKUECsbvZCQu7ikuEs1h+fs3+Qp+Fq8NK/@postini.com; Fri, 31 Aug 2012 12:22:13 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id D04F447; Fri, 31 Aug 2012 12:21:35 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 4953F49; Fri, 31 Aug 2012 08:31:53 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 9B55724C2E5; Fri, 31 Aug 2012 14:21:56 +0200 (CEST) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Fri, 31 Aug 2012 14:22:03 +0200 From: Ulf Hansson To: , Mike Turquette , Mike Turquette , Samuel Ortiz , Cc: Linus Walleij , Lee Jones , Philippe Begnic , Srinidhi Kasagar , Ulf Hansson Subject: [PATCH 2/4] clk: ux500: Support for prmcu_rate clock Date: Fri, 31 Aug 2012 14:21:29 +0200 Message-ID: <1346415691-13371-3-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com> References: <1346415691-13371-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQkW7NvMEyNX2NkH4vnYs8n9+ee3nyEC64fRK7/IguUd6h6X9xaFA53yK5TR3xncc1/0UFBx From: Ulf Hansson The prmcu_rate clock is not gateable and has a rate which only can be fetched. Signed-off-by: Ulf Hansson --- drivers/clk/ux500/clk-prcmu.c | 14 ++++++++++++++ drivers/clk/ux500/clk.h | 5 +++++ 2 files changed, 19 insertions(+) diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c index 1d779ad..930cdfe 100644 --- a/drivers/clk/ux500/clk-prcmu.c +++ b/drivers/clk/ux500/clk-prcmu.c @@ -153,6 +153,11 @@ static struct clk_ops clk_prcmu_gate_ops = { .recalc_rate = clk_prcmu_recalc_rate, }; +static struct clk_ops clk_prcmu_rate_ops = { + .is_enabled = clk_prcmu_is_enabled, + .recalc_rate = clk_prcmu_recalc_rate, +}; + static struct clk_ops clk_prcmu_opp_gate_ops = { .prepare = clk_prcmu_opp_prepare, .unprepare = clk_prcmu_opp_unprepare, @@ -228,6 +233,15 @@ struct clk *clk_reg_prcmu_gate(const char *name, &clk_prcmu_gate_ops); } +struct clk *clk_reg_prcmu_rate(const char *name, + const char *parent_name, + u8 cg_sel, + unsigned long flags) +{ + return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags, + &clk_prcmu_rate_ops); +} + struct clk *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h index 32085aa..836d7d1 100644 --- a/drivers/clk/ux500/clk.h +++ b/drivers/clk/ux500/clk.h @@ -35,6 +35,11 @@ struct clk *clk_reg_prcmu_gate(const char *name, u8 cg_sel, unsigned long flags); +struct clk *clk_reg_prcmu_rate(const char *name, + const char *parent_name, + u8 cg_sel, + unsigned long flags); + struct clk *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel,