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[203.254.224.24]) by mx.google.com with ESMTP id pf8si37966729pbc.319.2012.08.29.03.43.32; Wed, 29 Aug 2012 03:43:33 -0700 (PDT) Received-SPF: neutral (google.com: 203.254.224.24 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=neutral (google.com: 203.254.224.24 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) smtp.mail=thomas.abraham@linaro.org Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M9I008HZJ4KEG01@mailout1.samsung.com>; Wed, 29 Aug 2012 19:43:32 +0900 (KST) X-AuditID: cbfee61a-b7fc66d0000043b7-eb-503df253ac23 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id AC.92.17335.352FD305; Wed, 29 Aug 2012 19:43:32 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M9I00K0KJ3AVK60@mmp1.samsung.com>; Wed, 29 Aug 2012 19:43:31 +0900 (KST) From: Thomas Abraham To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, kgene.kim@samsung.com, girish.shivananjappa@linaro.org, jh80.chung@samsung.com, tgih.jun@samsung.com, patches@linaro.org Subject: [PATCH v4 1/3] ARM: Samsung: Add support for MSHC controller clocks Date: Wed, 29 Aug 2012 16:31:10 +0530 Message-id: <1346238072-7324-2-git-send-email-thomas.abraham@linaro.org> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1346238072-7324-1-git-send-email-thomas.abraham@linaro.org> References: <1346238072-7324-1-git-send-email-thomas.abraham@linaro.org> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jAd2QT7YBBh+uMVt8+XqCzWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DK+HqxhbnglmxF++8L7A2MC8W7GDk5JARMJA6+/ssM YYtJXLi3nq2LkYtDSGARo8TGw1NYQRJCAm1MEl/2ZoDYbAIGEo8WvmMHsUUENCSmdD1mB2lg FjjBKHHrxXuwBmEBH4k1Kx+zgdgsAqoSHzd+ZwGxeQU8JHY/eMsCsU1JYkPvUSYQm1PAU2LN l+tsEMs8JLYfOsQ4gZF3ASPDKkbR1ILkguKk9FxDveLE3OLSvHS95PzcTYxg/z+T2sG4ssHi EKMAB6MSD+8FbtsAIdbEsuLK3EOMEhzMSiK8qa+AQrwpiZVVqUX58UWlOanFhxilOViUxHn5 +wwDhATSE0tSs1NTC1KLYLJMHJxSDYwpfxent4l1abuLZXimG31cuiI3kOlyjWxyzBf9HckC osLzqhbLZcvyBLJadyT9XiX4YOX7Jev+m2+8z3PQ/FSGe9Slp+5nTgtLzz5wv6PZcUXbEr6o j8m3A+6+spep/HB0Z3igEuMS7SMcXifks9y/LrEr0GNPPrzwo3DWjAKJaOHpe7zlU5RYijMS DbWYi4oTAVj7OtT7AQAA X-Gm-Message-State: ALoCoQm3kS9Z/o05HYYADkrDOS8N3eXvw4DjLft+w0Fx/EfRdZwOC6198DowsteTcuDeK3lo0p/D Add clock instances for bus interface unit clock and card interface unit clock of the all four MSHC controller instances. Signed-off-by: Abhilash Kesavan Signed-off-by: Thomas Abraham --- arch/arm/mach-exynos/clock-exynos5.c | 45 ++++++++++++---------------------- 1 files changed, 16 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 3b00e29..16d8bef 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_peris_ctrl, .ctrlbit = (1 << 19), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.0", + .name = "biu", + .devname = "dw_mmc.0", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 12), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.1", + .name = "biu", + .devname = "dw_mmc.1", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 13), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.2", + .name = "biu", + .devname = "dw_mmc.2", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 14), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.3", + .name = "biu", + .devname = "dw_mmc.3", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 15), }, { - .name = "dwmci", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 16), - }, { .name = "sata", .devname = "ahci", .enable = exynos5_clk_ip_fsys_ctrl, @@ -1006,8 +1001,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { static struct clksrc_clk exynos5_clk_sclk_mmc0 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.0", + .name = "ciu", + .devname = "dw_mmc.0", .parent = &exynos5_clk_dout_mmc0.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -1017,8 +1012,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { static struct clksrc_clk exynos5_clk_sclk_mmc1 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.1", + .name = "ciu", + .devname = "dw_mmc.1", .parent = &exynos5_clk_dout_mmc1.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -1028,8 +1023,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { static struct clksrc_clk exynos5_clk_sclk_mmc2 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.2", + .name = "ciu", + .devname = "dw_mmc.2", .parent = &exynos5_clk_dout_mmc2.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1039,8 +1034,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.3", + .name = "ciu", + .devname = "dw_mmc.3", .parent = &exynos5_clk_dout_mmc3.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -1114,14 +1109,6 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = { static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { - .name = "sclk_dwmci", - .parent = &exynos5_clk_dout_mmc4.clk, - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 16), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 }, - }, { - .clk = { .name = "sclk_fimd", .devname = "s3cfb.1", .enable = exynos5_clksrc_mask_disp1_0_ctrl,