From patchwork Sun Aug 26 11:59:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thomas.abraham@linaro.org X-Patchwork-Id: 10960 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 69E0523E00 for ; Sun, 26 Aug 2012 11:41:29 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 0A041A180CD for ; Sun, 26 Aug 2012 11:41:05 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id j25so3780951iaf.11 for ; Sun, 26 Aug 2012 04:41:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-gm-message-state; bh=oWx4lE/9sTscD71M13IU/+vCvja2LrQgRHDcQkoOY1k=; b=EYPgdRkFGxM+ZVTFUSyzSfbDHS7e9vzJp+WcMmof2fAxRxKDnToOq87lhHwfO5L2EM QI/B8Y5CYjxriVtu8tcN2JClsMJpA3jwya06HriE9uKOI5yMT71cjonnGWxepa8VPL48 ZTqwiuHkAku8DjhbdxY4kExUVhQC+buRYddZEXKk5weq5KyBxG7WYvXII31afZNvQcti 0WdC2PweKGi5Eoo5awqR7j4RccF/6RvhkXNvJjYC+NYgvMVol8W1T6/mva1MQGVeRUWc 2bdl4kcPtwf0/+Zi9P6JgBMfNUhEx+k8g5lgi38/mwXt0VKSDu/9Idj2GSZBM6ahQhg/ CCuw== Received: by 10.50.159.196 with SMTP id xe4mr7131397igb.43.1345981288830; Sun, 26 Aug 2012 04:41:28 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp396589igc; Sun, 26 Aug 2012 04:41:28 -0700 (PDT) Received: by 10.68.227.70 with SMTP id ry6mr26374640pbc.53.1345981288086; Sun, 26 Aug 2012 04:41:28 -0700 (PDT) Received: from mailout2.samsung.com (mailout2.samsung.com. [203.254.224.25]) by mx.google.com with ESMTP id kc9si27253019pbc.115.2012.08.26.04.41.27; Sun, 26 Aug 2012 04:41:28 -0700 (PDT) Received-SPF: neutral (google.com: 203.254.224.25 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=neutral (google.com: 203.254.224.25 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) smtp.mail=thomas.abraham@linaro.org Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M9D008141SXU2C0@mailout2.samsung.com>; Sun, 26 Aug 2012 20:41:26 +0900 (KST) X-AuditID: cbfee61b-b7faf6d00000476a-f0-503a0b665725 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id DB.8A.18282.66B0A305; Sun, 26 Aug 2012 20:41:26 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M9D00JEH1SVN450@mmp2.samsung.com>; Sun, 26 Aug 2012 20:41:26 +0900 (KST) From: Thomas Abraham To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, cjb@laptop.org, kgene.kim@samsung.com, girish.shivananjappa@linaro.org, jh80.chung@samsung.com, tgih.jun@samsung.com, patches@linaro.org Subject: [PATCH v3 1/3] ARM: Samsung: Add support for MSHC controller clocks Date: Sun, 26 Aug 2012 17:29:29 +0530 Message-id: <1345982371-26483-2-git-send-email-thomas.abraham@linaro.org> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org> References: <1345982371-26483-1-git-send-email-thomas.abraham@linaro.org> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJJMWRmVeSWpSXmKPExsVy+t9jQd00bqsAg7uPtC2+fD3BZjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlfL3YwlxwS7ai/fcF9gbGheJdjJwcEgImEg9/LmKC sMUkLtxbz9bFyMUhJDCdUeLdy6ssEE4bk8SiN7NZQarYBAwkHi18xw5iiwhoSEzpeswOUsQs sJlRYsGDA8wgCWEBH4kt7zeAFbEIqEr8/b2REcTmFfCUOLn8AhvEOiWJDb1HwVZzCnhJLH+9 GqxXCKhm2bGdjBMYeRcwMqxiFE0tSC4oTkrPNdIrTswtLs1L10vOz93ECA6AZ9I7GFc1WBxi FOBgVOLhFSi1DBBiTSwrrsw9xCjBwawkwvt9P1CINyWxsiq1KD++qDQntfgQozQHi5I4L3+f YYCQQHpiSWp2ampBahFMlomDU6qB0fDSBo/NZ080v9bTPC156D1v1purPk9O1i3vU/Had6f5 4Y6IU52GK6ym1hU3P3n9+KTOA7ebW7w7P3ZtbLg8Z7N2uWFL9mb/mOKVeal8C77et1q4KXSi 7mQLmRU3lMouvhQUdrVPWyjlYPeicw1vVMXRcCmXY5NN763MUGJqKRO7LMzxZZtYnRJLcUai oRZzUXEiAKojjWr8AQAA X-Gm-Message-State: ALoCoQmHNMSW/LMITdIcxT3GQFdEoBX4NnYBb0tFXsQ4UFSMGwbiLxSdkH9Rnygl+LqpIfIbD9KJ Add clock instances for bus interface unit clock and card interface unit clock of the all four MSHC controller instances. Signed-off-by: Abhilash Kesavan Signed-off-by: Thomas Abraham --- arch/arm/mach-exynos/clock-exynos5.c | 45 ++++++++++++---------------------- 1 files changed, 16 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 3b00e29..16d8bef 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -564,35 +564,30 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_peris_ctrl, .ctrlbit = (1 << 19), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.0", + .name = "biu", + .devname = "dw_mmc.0", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 12), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.1", + .name = "biu", + .devname = "dw_mmc.1", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 13), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.2", + .name = "biu", + .devname = "dw_mmc.2", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 14), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.3", + .name = "biu", + .devname = "dw_mmc.3", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 15), }, { - .name = "dwmci", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 16), - }, { .name = "sata", .devname = "ahci", .enable = exynos5_clk_ip_fsys_ctrl, @@ -1006,8 +1001,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { static struct clksrc_clk exynos5_clk_sclk_mmc0 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.0", + .name = "ciu", + .devname = "dw_mmc.0", .parent = &exynos5_clk_dout_mmc0.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -1017,8 +1012,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { static struct clksrc_clk exynos5_clk_sclk_mmc1 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.1", + .name = "ciu", + .devname = "dw_mmc.1", .parent = &exynos5_clk_dout_mmc1.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -1028,8 +1023,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { static struct clksrc_clk exynos5_clk_sclk_mmc2 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.2", + .name = "ciu", + .devname = "dw_mmc.2", .parent = &exynos5_clk_dout_mmc2.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -1039,8 +1034,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.3", + .name = "ciu", + .devname = "dw_mmc.3", .parent = &exynos5_clk_dout_mmc3.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -1114,14 +1109,6 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = { static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { - .name = "sclk_dwmci", - .parent = &exynos5_clk_dout_mmc4.clk, - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 16), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 }, - }, { - .clk = { .name = "sclk_fimd", .devname = "s3cfb.1", .enable = exynos5_clksrc_mask_disp1_0_ctrl,