From patchwork Thu May 17 16:35:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thomas.abraham@linaro.org X-Patchwork-Id: 8764 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id ECF0A23E23 for ; Thu, 17 May 2012 16:22:40 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id A6907A1843F for ; Thu, 17 May 2012 16:22:40 +0000 (UTC) Received: by ggnf1 with SMTP id f1so2399518ggn.11 for ; Thu, 17 May 2012 09:22:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=e1Ula+mPVAXDqLTIO8/4T/WDB6kDtjnixkEa/sNvnq4=; b=SFNOMrUN8Kh/7/2K70AB7EjQ9eFF/YMrFe2R6Ow2bPWEnrZ53fDKkhHFEs1xfV0teg QCGgY3KE6p45LgzKTTuOSqAaO1Jv0GrEL9ABrSJ46fyZT83IFLATA6Ce74iPrvjrBBCd gduG6CkEt40aFzSngsTLTu2eC1yhYygs94YHoZ8a4s31ky6AWjeCdILrc5slsV6FPkRp cK4mvQRdM7tNlKXE3yIfGr2NX17yygRNU9czz0u1njWB821mq95bB2CuUxtu+rj93r2f 9cJwG2m+A0stUEx/YTVd5/rIxLyf6pV1HH2eOIpbn72dhCyGO0NiynC9vOKBXvxNa0e1 4HeA== Received: by 10.50.195.234 with SMTP id ih10mr6290824igc.0.1337271759455; Thu, 17 May 2012 09:22:39 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp39862ibd; Thu, 17 May 2012 09:22:38 -0700 (PDT) Received: by 10.68.232.135 with SMTP id to7mr28466082pbc.143.1337271758746; Thu, 17 May 2012 09:22:38 -0700 (PDT) Received: from mailout1.samsung.com (mailout1.samsung.com. [203.254.224.24]) by mx.google.com with ESMTP id sp3si5680946pbc.118.2012.05.17.09.22.38; Thu, 17 May 2012 09:22:38 -0700 (PDT) Received-SPF: neutral (google.com: 203.254.224.24 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=neutral (google.com: 203.254.224.24 is neither permitted nor denied by best guess record for domain of thomas.abraham@linaro.org) smtp.mail=thomas.abraham@linaro.org Received: from epcpsbgm2.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M4600CUCDHLKF50@mailout1.samsung.com> for patches@linaro.org; Fri, 18 May 2012 01:22:37 +0900 (KST) X-AuditID: cbfee61b-b7bb6ae0000006fb-2e-4fb525cdb409 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (MMPCPMTA) with SMTP id DB.43.01787.DC525BF4; Fri, 18 May 2012 01:22:37 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M4600C3IDGOZP50@mmp1.samsung.com> for patches@linaro.org; Fri, 18 May 2012 01:22:37 +0900 (KST) From: Thomas Abraham To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com, patches@linaro.org Subject: [PATCH 1/3] ARM: Exynos5: Add support for MSHC controller clocks Date: Thu, 17 May 2012 22:05:32 +0530 Message-id: <1337272534-30370-2-git-send-email-thomas.abraham@linaro.org> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1337272534-30370-1-git-send-email-thomas.abraham@linaro.org> References: <1337272534-30370-1-git-send-email-thomas.abraham@linaro.org> X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQlCyDtlBz3j33JhcLcj2B1OKbOCnAhdkAWSqqZId2WtY7Rr3FnFSwe/6U+M5iaTBQiTYEwp Add clock instances for bus interface unit clock and card interface unit clock of the all four MSHC controller instances. Signed-off-by: Abhilash Kesavan Signed-off-by: Thomas Abraham --- arch/arm/mach-exynos/clock-exynos5.c | 45 ++++++++++++---------------------- 1 files changed, 16 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 7c0f810..4e17131 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -524,35 +524,30 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_peris_ctrl, .ctrlbit = (1 << 19), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.0", + .name = "biu", + .devname = "dw_mmc.0", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 12), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.1", + .name = "biu", + .devname = "dw_mmc.1", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 13), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.2", + .name = "biu", + .devname = "dw_mmc.2", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 14), }, { - .name = "hsmmc", - .devname = "exynos4-sdhci.3", + .name = "biu", + .devname = "dw_mmc.3", .parent = &exynos5_clk_aclk_200.clk, .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 15), }, { - .name = "dwmci", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 16), - }, { .name = "sata", .devname = "ahci", .enable = exynos5_clk_ip_fsys_ctrl, @@ -882,8 +877,8 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { static struct clksrc_clk exynos5_clk_sclk_mmc0 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.0", + .name = "ciu", + .devname = "dw_mmc.0", .parent = &exynos5_clk_dout_mmc0.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 0), @@ -893,8 +888,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { static struct clksrc_clk exynos5_clk_sclk_mmc1 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.1", + .name = "ciu", + .devname = "dw_mmc.1", .parent = &exynos5_clk_dout_mmc1.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 4), @@ -904,8 +899,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { static struct clksrc_clk exynos5_clk_sclk_mmc2 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.2", + .name = "ciu", + .devname = "dw_mmc.2", .parent = &exynos5_clk_dout_mmc2.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 8), @@ -915,8 +910,8 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .clk = { - .name = "sclk_mmc", - .devname = "exynos4-sdhci.3", + .name = "ciu", + .devname = "dw_mmc.3", .parent = &exynos5_clk_dout_mmc3.clk, .enable = exynos5_clksrc_mask_fsys_ctrl, .ctrlbit = (1 << 12), @@ -927,14 +922,6 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = { static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { - .name = "sclk_dwmci", - .parent = &exynos5_clk_dout_mmc4.clk, - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 16), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 }, - }, { - .clk = { .name = "sclk_fimd", .devname = "s3cfb.1", .enable = exynos5_clksrc_mask_disp1_0_ctrl,