From patchwork Fri Apr 27 07:02:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 8271 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C386023E42 for ; Fri, 27 Apr 2012 07:03:22 +0000 (UTC) Received: from mail-ob0-f180.google.com (mail-ob0-f180.google.com [209.85.214.180]) by fiordland.canonical.com (Postfix) with ESMTP id 6CE3BA18363 for ; Fri, 27 Apr 2012 07:03:22 +0000 (UTC) Received: by mail-ob0-f180.google.com with SMTP id wc20so829790obb.11 for ; Fri, 27 Apr 2012 00:03:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :x-spamscore:x-bigfish:x-forefront-antispam-report:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:content-transfer-encoding:x-originatororg :x-gm-message-state; bh=DF0XKXcsHliZCrAPt4rrtoNiytgkaU3blaTUD/Mt2GM=; b=pjNz/t12WXo8tbe03Iy9S+s48ov2R/A1pJ6SKndxWnwTukiKo24FvgJ9eSJfNSmRgk fm2GeBFvp0yK05xYL23XN9RCeVqi4h50Kpy7CHhvQLfQ3VvIjurC9JzKPuskcrQvL+C7 OZ3YbPxeD+FOTzyASnAPlTbk+4TdUm4iyP4WY11GOX3fRHT6DvuOSUdrwY4r/Ejh9jjy FLfy2PLSysvapfMThDhJlwvu66vYTt9oV/8sHytk/rfIZGDzBt4OiJQSyL0UNWphltUe stvj9MVybaNHjBK+sDu1tl70Ei4HrJW2I/MojlIiFHgAcTHQXzW7iOf4U5S8aK3x7SRU nc7g== Received: by 10.50.154.167 with SMTP id vp7mr789521igb.55.1335510202080; Fri, 27 Apr 2012 00:03:22 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp5430ibt; Fri, 27 Apr 2012 00:03:21 -0700 (PDT) Received: by 10.180.97.41 with SMTP id dx9mr3040932wib.9.1335510200918; Fri, 27 Apr 2012 00:03:20 -0700 (PDT) Received: from tx2outboundpool.messaging.microsoft.com (tx2ehsobe002.messaging.microsoft.com. [65.55.88.12]) by mx.google.com with ESMTPS id o6si6712717wee.144.2012.04.27.00.03.20 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 27 Apr 2012 00:03:20 -0700 (PDT) Received-SPF: neutral (google.com: 65.55.88.12 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) client-ip=65.55.88.12; Authentication-Results: mx.google.com; spf=neutral (google.com: 65.55.88.12 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) smtp.mail=B20223@freescale.com Received: from mail86-tx2-R.bigfish.com (10.9.14.244) by TX2EHSOBE004.bigfish.com (10.9.40.24) with Microsoft SMTP Server id 14.1.225.23; Fri, 27 Apr 2012 07:03:17 +0000 Received: from mail86-tx2 (localhost [127.0.0.1]) by mail86-tx2-R.bigfish.com (Postfix) with ESMTP id DDF3E1A049E; Fri, 27 Apr 2012 07:03:16 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzc89bhzz1202hzz8275bhz2dh2a8h668h839h93fhd24he5bh) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail86-tx2 (localhost.localdomain [127.0.0.1]) by mail86-tx2 (MessageSwitch) id 1335510194393900_11839; Fri, 27 Apr 2012 07:03:14 +0000 (UTC) Received: from TX2EHSMHS039.bigfish.com (unknown [10.9.14.244]) by mail86-tx2.bigfish.com (Postfix) with ESMTP id 4E371A0043; Fri, 27 Apr 2012 07:03:14 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS039.bigfish.com (10.9.99.139) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 27 Apr 2012 07:03:14 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.355.3; Fri, 27 Apr 2012 02:03:15 -0500 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id q3R737LJ008722; Fri, 27 Apr 2012 02:03:11 -0500 (CDT) From: Richard Zhao To: , , CC: , , , , , , , Richard Zhao , =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Subject: [PATCH 01/11] dma: imx-sdma: make channel0 operations atomic Date: Fri, 27 Apr 2012 15:02:55 +0800 Message-ID: <1335510185-7906-2-git-send-email-richard.zhao@freescale.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1335510185-7906-1-git-send-email-richard.zhao@freescale.com> References: <1335510185-7906-1-git-send-email-richard.zhao@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-Gm-Message-State: ALoCoQn9vAp8uErc+6l12PrZKb4H5SY7vfzEJDNrU8gkMM6/rFkncdf9NDGUys5lZHA3ZnbWaSAH device_prep_dma_cyclic may be call in audio trigger function which is atomic context, so we make it atomic too. - change channel0 lock to spinlock. - Use polling to wait for channel0 finish running. Signed-off-by: Lothar Waßmann Signed-off-by: Richard Zhao --- drivers/dma/imx-sdma.c | 57 +++++++++++++++++++++++++++-------------------- 1 files changed, 33 insertions(+), 24 deletions(-) diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index fddccae..fc49ffa 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include @@ -324,7 +324,7 @@ struct sdma_engine { struct dma_device dma_device; struct clk *clk_ipg; struct clk *clk_ahb; - struct mutex channel_0_lock; + spinlock_t channel_0_lock; struct sdma_script_start_addrs *script_addrs; }; @@ -402,19 +402,31 @@ static void sdma_enable_channel(struct sdma_engine *sdma, int channel) } /* - * sdma_run_channel - run a channel and wait till it's done + * sdma_run_channel0 - run a channel and wait till it's done */ -static int sdma_run_channel(struct sdma_channel *sdmac) +static int sdma_run_channel0(struct sdma_channel *sdmac) { struct sdma_engine *sdma = sdmac->sdma; int channel = sdmac->channel; int ret; + unsigned long timeout = 500; - init_completion(&sdmac->done); - + if (channel) + return -EINVAL; sdma_enable_channel(sdma, channel); - ret = wait_for_completion_timeout(&sdmac->done, HZ); + while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) { + if (timeout-- <= 0) + break; + udelay(1); + } + + if (ret) { + /* Clear the interrupt status */ + writel_relaxed(ret, sdma->regs + SDMA_H_INTR); + } else { + dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); + } return ret ? 0 : -ETIMEDOUT; } @@ -426,17 +438,17 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, void *buf_virt; dma_addr_t buf_phys; int ret; - - mutex_lock(&sdma->channel_0_lock); + unsigned long flags; buf_virt = dma_alloc_coherent(NULL, size, &buf_phys, GFP_KERNEL); if (!buf_virt) { - ret = -ENOMEM; - goto err_out; + return -ENOMEM; } + spin_lock_irqsave(&sdma->channel_0_lock, flags); + bd0->mode.command = C0_SETPM; bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; bd0->mode.count = size / 2; @@ -445,12 +457,11 @@ static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, memcpy(buf_virt, buf, size); - ret = sdma_run_channel(&sdma->channel[0]); + ret = sdma_run_channel0(&sdma->channel[0]); - dma_free_coherent(NULL, size, buf_virt, buf_phys); + spin_unlock_irqrestore(&sdma->channel_0_lock, flags); -err_out: - mutex_unlock(&sdma->channel_0_lock); + dma_free_coherent(NULL, size, buf_virt, buf_phys); return ret; } @@ -539,10 +550,6 @@ static void mxc_sdma_handle_channel(struct sdma_channel *sdmac) { complete(&sdmac->done); - /* not interested in channel 0 interrupts */ - if (sdmac->channel == 0) - return; - if (sdmac->flags & IMX_DMA_SG_LOOP) sdma_handle_channel_loop(sdmac); else @@ -555,6 +562,8 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) unsigned long stat; stat = readl_relaxed(sdma->regs + SDMA_H_INTR); + /* not interested in channel 0 interrupts */ + stat &= ~1; writel_relaxed(stat, sdma->regs + SDMA_H_INTR); while (stat) { @@ -660,6 +669,7 @@ static int sdma_load_context(struct sdma_channel *sdmac) struct sdma_context_data *context = sdma->context; struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; int ret; + unsigned long flags; if (sdmac->direction == DMA_DEV_TO_MEM) { load_address = sdmac->pc_from_device; @@ -677,7 +687,7 @@ static int sdma_load_context(struct sdma_channel *sdmac) dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); - mutex_lock(&sdma->channel_0_lock); + spin_lock_irqsave(&sdma->channel_0_lock, flags); memset(context, 0, sizeof(*context)); context->channel_state.pc = load_address; @@ -696,10 +706,9 @@ static int sdma_load_context(struct sdma_channel *sdmac) bd0->mode.count = sizeof(*context) / 4; bd0->buffer_addr = sdma->context_phys; bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; + ret = sdma_run_channel0(&sdma->channel[0]); - ret = sdma_run_channel(&sdma->channel[0]); - - mutex_unlock(&sdma->channel_0_lock); + spin_unlock_irqrestore(&sdma->channel_0_lock, flags); return ret; } @@ -1305,7 +1314,7 @@ static int __init sdma_probe(struct platform_device *pdev) if (!sdma) return -ENOMEM; - mutex_init(&sdma->channel_0_lock); + spin_lock_init(&sdma->channel_0_lock); sdma->dev = &pdev->dev;