From patchwork Mon Apr 2 17:00:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Liu X-Patchwork-Id: 7575 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A098D19920F for ; Mon, 2 Apr 2012 17:01:07 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 44FBFA18282 for ; Mon, 2 Apr 2012 17:01:07 +0000 (UTC) Received: by iage36 with SMTP id e36so6198239iag.11 for ; Mon, 02 Apr 2012 10:01:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=7Kq3h0+r8agIelN5xZ7nJxKdNCrGe7nR6Gbjwr7Fxd0=; b=l4uNBL2nC+Qg8djSjsYqivNEjH+iehJo/59MENxhRQIv5cHpafka0KEi30Tko+s6Ih e5HWGG+BA8tLQfMG9xaGba5q/R6dwu2ObUw6xUnk3ZAKrtcvAxeVXLInJBvYUkJ01NvQ tSWWR+JEuypNPniMsJ/US0NDmk5awkIC6E7vK9i+nLiSIbB3/z8lZ+jBLq6JZX/QT9NQ VwQerxpRfGqTqpaaa1Obl0k/b/GDqfcNpyr/NqqRqo9xDl4Of1HcKJw2ZlRQiGduJH8H xL2ht6vA7kyTf7nfAvOujrRWMHcgSO3tr4w9N8/Y9XwH1DLi75SQaDucBMflw6uGW99n RFAw== Received: by 10.42.203.148 with SMTP id fi20mr5070017icb.10.1333386066406; Mon, 02 Apr 2012 10:01:06 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp121150ibw; Mon, 2 Apr 2012 10:01:05 -0700 (PDT) Received: by 10.68.72.138 with SMTP id d10mr22309383pbv.15.1333386064749; Mon, 02 Apr 2012 10:01:04 -0700 (PDT) Received: from mail-pz0-f44.google.com (mail-pz0-f44.google.com [209.85.210.44]) by mx.google.com with ESMTPS id o4si405542pbi.295.2012.04.02.10.01.03 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 02 Apr 2012 10:01:04 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.44 is neither permitted nor denied by best guess record for domain of paul.liu@linaro.org) client-ip=209.85.210.44; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.44 is neither permitted nor denied by best guess record for domain of paul.liu@linaro.org) smtp.mail=paul.liu@linaro.org Received: by dadz14 with SMTP id z14so11660911dad.17 for ; Mon, 02 Apr 2012 10:01:03 -0700 (PDT) Received: by 10.68.230.70 with SMTP id sw6mr21756405pbc.101.1333386063375; Mon, 02 Apr 2012 10:01:03 -0700 (PDT) Received: from freya.lan (host-77.138-185-111.static.totalbb.net.tw. [111.185.138.77]) by mx.google.com with ESMTPS id a9sm6068854pbr.73.2012.04.02.10.01.00 (version=SSLv3 cipher=OTHER); Mon, 02 Apr 2012 10:01:02 -0700 (PDT) From: "Ying-Chun Liu (PaulLiu)" To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linaro-dev@lists.linaro.org, patches@linaro.org, "Ying-Chun Liu (PaulLiu)" , Richard Zhao , Shawn Guo Subject: [PATCH v3] ARM: dts: imx6q: add anatop regulators Date: Tue, 3 Apr 2012 01:00:51 +0800 Message-Id: <1333386051-4301-1-git-send-email-paul.liu@linaro.org> X-Mailer: git-send-email 1.7.9.1 X-Gm-Message-State: ALoCoQmyyHUx4N9gdQmuukHEsw9g8HghVYktNiKHnlp4fBXFlmztCcOJSCuYyJTH/CXHG2/BI6U9 From: "Ying-Chun Liu (PaulLiu)" Add anatop regulators to imx6q.dtsi for all imx6q platforms. Signed-off-by: Ying-Chun Liu (PaulLiu) Signed-off-by: Richard Zhao Cc: Shawn Guo --- arch/arm/boot/dts/imx6q.dtsi | 84 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 84 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 263e8f3..33e1e14 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -346,6 +346,90 @@ compatible = "fsl,imx6q-anatop"; reg = <0x020c8000 0x1000>; interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; + + regulator-1p1@110 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1375000>; + regulator-always-on; + anatop-reg-offset = <0x110>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <4>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1375000>; + }; + + regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + }; + + regulator-2p5@130 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; + anatop-reg-offset = <0x130>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2000000>; + anatop-max-voltage = <2750000>; + }; + + regulator-vddcore@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + regulator-vddpu@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + regulator-vddsoc@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; }; usbphy@020c9000 { /* USBPHY1 */