From patchwork Fri Mar 30 13:46:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Liu X-Patchwork-Id: 7549 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4000123E29 for ; Fri, 30 Mar 2012 13:47:02 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id CF879A18709 for ; Fri, 30 Mar 2012 13:47:01 +0000 (UTC) Received: by iage36 with SMTP id e36so1397284iag.11 for ; Fri, 30 Mar 2012 06:47:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :mime-version:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=/N7EhPx9Vj/FE4AAG6/0Dw0EbtpyDWPCcGyoppBGX5I=; b=nY+Ye52fhifvguLmPrFDj3jrqbcbeAaH7oQRi7WvPmmn/xmBSnac7No1cm9z/V6xYW cDnj/RoDvkZYeiQzeG2q0rJOheZMfteLLtB9g9GkO6FDEGYLS2OgRZX6IE9ea3GEHBhW T5qxT7Aznh5VvXVD9M5gzGpF3FqrA7Amt21HQ3mC7BnT1D1MtKRbx8sNcTa5cNd6WAlV 5Zp/JRcj0yTkzrdsN98++cRFMYkypG3zS79TYPicGKZWucwkgu6VCi7PP+YOePp7je8M lJceMIjkB6z0EO6y9aBJtT4zpnlo77pFqegonNw38OETIntjHj24mapbUDdOEmNMvTtQ NmCQ== Received: by 10.50.186.161 with SMTP id fl1mr1372431igc.44.1333115221250; Fri, 30 Mar 2012 06:47:01 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp23519ibw; Fri, 30 Mar 2012 06:47:00 -0700 (PDT) Received: by 10.236.157.105 with SMTP id n69mr2021802yhk.38.1333115220003; Fri, 30 Mar 2012 06:47:00 -0700 (PDT) Received: from mail-yw0-f50.google.com (mail-yw0-f50.google.com [209.85.213.50]) by mx.google.com with ESMTPS id p6si3729566ani.64.2012.03.30.06.46.59 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:46:59 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.213.50 is neither permitted nor denied by best guess record for domain of paul.liu@linaro.org) client-ip=209.85.213.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.213.50 is neither permitted nor denied by best guess record for domain of paul.liu@linaro.org) smtp.mail=paul.liu@linaro.org Received: by yhjj63 with SMTP id j63so349125yhj.37 for ; Fri, 30 Mar 2012 06:46:59 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.125.228 with SMTP id mt4mr9368483pbb.105.1333115219225; Fri, 30 Mar 2012 06:46:59 -0700 (PDT) Received: from freya.lan (host-77.138-185-111.static.totalbb.net.tw. [111.185.138.77]) by mx.google.com with ESMTPS id x1sm7429159pbp.50.2012.03.30.06.46.57 (version=SSLv3 cipher=OTHER); Fri, 30 Mar 2012 06:46:58 -0700 (PDT) From: "Ying-Chun Liu (PaulLiu)" To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linaro-dev@lists.linaro.org, patches@linaro.org, "Ying-Chun Liu (PaulLiu)" , Richard Zhao , Shawn Guo Subject: [PATCH v2] ARM: dts: imx6q: add anatop regulators Date: Fri, 30 Mar 2012 21:46:53 +0800 Message-Id: <1333115213-28922-1-git-send-email-paul.liu@linaro.org> X-Mailer: git-send-email 1.7.9.1 X-Gm-Message-State: ALoCoQky/zI+rHMS+/EhvCXCqUukAx1XT4pDSg6gwUZ7KWCN9790Fbi+4BmTR6P25hv5a9NPIbeh From: "Ying-Chun Liu (PaulLiu)" Add anatop regulators to imx6q.dtsi for all imx6q platforms. Signed-off-by: Ying-Chun Liu (PaulLiu) Signed-off-by: Richard Zhao Cc: Shawn Guo --- arch/arm/boot/dts/imx6q.dtsi | 86 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 86 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 263e8f3..79f59e7 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -346,6 +346,92 @@ compatible = "fsl,imx6q-anatop"; reg = <0x020c8000 0x1000>; interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; + #address-cells = <1>; + #size-cells = <0>; + + regulator-1p1@110 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1375000>; + regulator-always-on; + anatop-reg-offset = <0x110>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <4>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1375000>; + }; + + regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + }; + + regulator-2p5@130 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; + anatop-reg-offset = <0x130>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2000000>; + anatop-max-voltage = <2750000>; + }; + + regulator-vddcore@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + regulator-vddpu@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + regulator-vddsoc@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; }; usbphy@020c9000 { /* USBPHY1 */