From patchwork Wed Mar 14 08:22:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 7277 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id F248523E0E for ; Wed, 14 Mar 2012 08:23:21 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id B7D16A186F0 for ; Wed, 14 Mar 2012 08:23:21 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so2733695iag.11 for ; Wed, 14 Mar 2012 01:23:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :x-spamscore:x-bigfish:x-forefront-antispam-report :x-fb-domain-ip-match:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:mime-version:content-type:x-originatororg :x-gm-message-state; bh=KyyzTrOULC2TE15fJBZl5I8gBEPamz6cAFchrT58BIQ=; b=WWe7cN1NpC/ulBeJRL5QVRu9UwW/nVXvoJNRLhPxX4fkfNPl+J6cfE0hfKWfDcGD3A d26jXqyvUSHk3algI+GG2ugyUPXHeNUdEPgF0U5W51FEqIzBKqgUOwTrZj4WiZ5cQZnX CyDf/Vq6wyusOqPXIMYeW7rrkmN6di5ssNwCrduE/4w6uC44F7tOfesfBwBiKHUFCpjg o14ZDlqD2TfoKLg1tBrtTcLXViM1HFodmQihaOj8UiRXa5rWE10/fJIRpwFMABmCINtm rfDEKtqZHynyq5FSc7YjSjU7FeEgBJC3zabk9/komqA7ddXERiHLQRDyPx7BTnGR9j2l hwBg== Received: by 10.50.183.137 with SMTP id em9mr9936211igc.58.1331713401442; Wed, 14 Mar 2012 01:23:21 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp4323ibg; Wed, 14 Mar 2012 01:23:20 -0700 (PDT) Received: by 10.180.79.231 with SMTP id m7mr4030997wix.11.1331713399861; Wed, 14 Mar 2012 01:23:19 -0700 (PDT) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe002.messaging.microsoft.com. [213.199.154.205]) by mx.google.com with ESMTPS id ea7si23021886wib.28.2012.03.14.01.23.19 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Mar 2012 01:23:19 -0700 (PDT) Received-SPF: neutral (google.com: 213.199.154.205 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) client-ip=213.199.154.205; Authentication-Results: mx.google.com; spf=neutral (google.com: 213.199.154.205 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) smtp.mail=richard.zhao@linaro.org Received: from mail72-am1-R.bigfish.com (10.3.201.236) by AM1EHSOBE002.bigfish.com (10.3.204.22) with Microsoft SMTP Server id 14.1.225.23; Wed, 14 Mar 2012 08:23:20 +0000 Received: from mail72-am1 (localhost [127.0.0.1]) by mail72-am1-R.bigfish.com (Postfix) with ESMTP id 3A3D3A03F7; Wed, 14 Mar 2012 08:23:20 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zcb8kzzz1202hzz8275dhz2dh87h2a8h668h839hd24h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail72-am1 (localhost.localdomain [127.0.0.1]) by mail72-am1 (MessageSwitch) id 1331713397982902_15153; Wed, 14 Mar 2012 08:23:17 +0000 (UTC) Received: from AM1EHSMHS004.bigfish.com (unknown [10.3.201.252]) by mail72-am1.bigfish.com (Postfix) with ESMTP id 3096B4006B; Wed, 14 Mar 2012 08:23:17 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS004.bigfish.com (10.3.207.104) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 14 Mar 2012 08:23:12 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.355.3; Wed, 14 Mar 2012 03:23:09 -0500 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id q2E8N3sQ005356; Wed, 14 Mar 2012 03:23:07 -0500 (CDT) From: Richard Zhao To: CC: , , , Richard Zhao Subject: [PATCH 2/2] ARM: imx6q: change pll1 rate when change arm_clk rate Date: Wed, 14 Mar 2012 16:22:59 +0800 Message-ID: <1331713379-8437-3-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org> References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-Gm-Message-State: ALoCoQnyVqIC1/JegtWAZ/hFkl7xsAiX9CBP2k5fXYVpMGXyE/8RwIdmGpkEcFNsL/MVezzjpAVS Add arm_clk's own get_rate/set_rate/round_rate functions. set_rate steps: - reparent pll1_sw_clk to pll2_pfd_400m or osc_clk - disable pll1_sys - set pll1_sys rate - enable pll1_sys - reparent pll1_sw_clk back to pll1_sys Signed-off-by: Richard Zhao --- arch/arm/mach-imx/clock-imx6q.c | 76 ++++++++++++++++++++++++++++++++++++++- 1 files changed, 75 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index 3d5dc56..e601f52 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c @@ -1782,7 +1782,6 @@ DEF_NG_CLK(periph2_pre_clk, &pll2_bus); DEF_NG_CLK(periph2_clk, &periph2_pre_clk); DEF_NG_CLK(axi_clk, &periph_clk); DEF_NG_CLK(emi_clk, &axi_clk); -DEF_NG_CLK(arm_clk, &pll1_sw_clk); DEF_NG_CLK(ahb_clk, &periph_clk); DEF_NG_CLK(ipg_clk, &ahb_clk); DEF_NG_CLK(ipg_perclk, &ipg_clk); @@ -1873,6 +1872,81 @@ DEF_CLK(emi_slow_clk, CCGR6, CG5, &axi_clk, NULL); DEF_CLK(vdo_axi_clk, CCGR6, CG6, &axi_clk, NULL); DEF_CLK(vpu_clk, CCGR6, CG7, &axi_clk, NULL); +static unsigned long arm_clk_get_rate(struct clk *clk) +{ + unsigned long parent_rate = clk_get_rate(clk->parent); + u32 reg, div; + + reg = readl_relaxed(CACRR); + div = (reg & BM_CACRR_ARM_PODF) >> BP_CACRR_ARM_PODF; + + return parent_rate / (div + 1); +} +static int arm_clk_bestdiv(unsigned long rate, unsigned long *prate) +{ + u32 i, maxdiv, bestdiv = 0; + unsigned long parent_rate, best = 0, now; + + *prate = 0; + maxdiv = (BM_CACRR_ARM_PODF >> BP_CACRR_ARM_PODF) + 1; + for (i = 1; i <= maxdiv; i++) { + int div; + parent_rate = clk_round_rate(&pll1_sys, rate * i); + div = parent_rate / rate; + div = div > maxdiv ? maxdiv : div; + div = div < 1 ? 1 : div; + now = parent_rate / div; + + if (now <= rate && now >= best) { + bestdiv = div; + best = now; + *prate = parent_rate; + if (now == rate) + break; + } + } + return bestdiv; +} + +static int arm_clk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + unsigned long parent_rate; + div = arm_clk_bestdiv(rate, &parent_rate); + + if (pll2_pfd_400m.usecount > 0) + pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400m); + else + pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk); + pll1_sys.disable(&pll1_sys); + pll1_sys.set_rate(&pll1_sys, parent_rate); + pll1_sys.enable(&pll1_sys); + pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys); + + reg = readl_relaxed(CACRR); + reg &= ~BM_CACRR_ARM_PODF; + reg |= (div - 1) << BP_CACRR_ARM_PODF; + writel_relaxed(reg, CACRR); + + return 0; +} + +static unsigned long arm_clk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long div, parent_rate; + + div = arm_clk_bestdiv(rate, &parent_rate); + return parent_rate / div; +} + +static struct clk arm_clk = { + .get_rate = arm_clk_get_rate, + .set_rate = arm_clk_set_rate, + .round_rate = arm_clk_round_rate, + .set_parent = _clk_set_parent, + .parent = &pll1_sw_clk, +}; + static int pcie_clk_enable(struct clk *clk) { u32 val;