From patchwork Thu Dec 22 12:23:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Chen X-Patchwork-Id: 5954 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id AEDD823E01 for ; Thu, 22 Dec 2011 12:23:55 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 8C447A1860C for ; Thu, 22 Dec 2011 12:23:55 +0000 (UTC) Received: by eaac11 with SMTP id c11so5686079eaa.11 for ; Thu, 22 Dec 2011 04:23:55 -0800 (PST) Received: by 10.205.120.14 with SMTP id fw14mr2997831bkc.53.1324556635334; Thu, 22 Dec 2011 04:23:55 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs64176bkc; Thu, 22 Dec 2011 04:23:54 -0800 (PST) Received: by 10.227.206.10 with SMTP id fs10mr10296209wbb.13.1324556633201; Thu, 22 Dec 2011 04:23:53 -0800 (PST) Received: from AM1EHSOBE006.bigfish.com (am1ehsobe006.messaging.microsoft.com. [213.199.154.209]) by mx.google.com with ESMTPS id h17si4426588wee.27.2011.12.22.04.23.52 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Dec 2011 04:23:53 -0800 (PST) Received-SPF: neutral (google.com: 213.199.154.209 is neither permitted nor denied by best guess record for domain of jason.chen@linaro.org) client-ip=213.199.154.209; Authentication-Results: mx.google.com; spf=neutral (google.com: 213.199.154.209 is neither permitted nor denied by best guess record for domain of jason.chen@linaro.org) smtp.mail=jason.chen@linaro.org Received: from mail72-am1-R.bigfish.com (10.3.201.251) by AM1EHSOBE006.bigfish.com (10.3.204.26) with Microsoft SMTP Server id 14.1.225.23; Thu, 22 Dec 2011 12:23:41 +0000 Received: from mail72-am1 (localhost [127.0.0.1]) by mail72-am1-R.bigfish.com (Postfix) with ESMTP id 04EF770050A; Thu, 22 Dec 2011 12:23:22 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail72-am1 (localhost.localdomain [127.0.0.1]) by mail72-am1 (MessageSwitch) id 1324556601628326_20043; Thu, 22 Dec 2011 12:23:21 +0000 (UTC) Received: from AM1EHSMHS017.bigfish.com (unknown [10.3.201.253]) by mail72-am1.bigfish.com (Postfix) with ESMTP id 95B12520047; Thu, 22 Dec 2011 12:23:21 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS017.bigfish.com (10.3.207.155) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 22 Dec 2011 12:23:41 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.355.3; Thu, 22 Dec 2011 06:23:50 -0600 Received: from weitway.ap.freescale.net (weitway.ap.freescale.net [10.192.242.173]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pBMCNlxJ027812; Thu, 22 Dec 2011 06:23:48 -0600 (CST) From: Jason Chen To: CC: , , Subject: [PATCH] arm/imx6q: add clock debugfs support Date: Thu, 22 Dec 2011 20:23:45 +0800 Message-ID: <1324556625-28192-1-git-send-email-jason.chen@linaro.org> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Signed-off-by: Jason Chen --- arch/arm/mach-imx/clock-imx6q.c | 24 +++++++++++++++++++++++- 1 files changed, 23 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index 9273c2a..840ab8d 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c @@ -335,6 +335,12 @@ #define FREQ_650M 650000000 #define FREQ_1300M 1300000000 +#ifdef CONFIG_CLK_DEBUG +#define __INIT_CLK_DEBUG(n) .name = #n, +#else +#define __INIT_CLK_DEBUG(n) +#endif + static struct clk pll1_sys; static struct clk pll2_bus; static struct clk pll3_usb_otg; @@ -415,14 +421,17 @@ static unsigned long get_low_reference_clock_rate(struct clk *clk) } static struct clk ckil_clk = { + __INIT_CLK_DEBUG(ckil_clk) .get_rate = get_low_reference_clock_rate, }; static struct clk ckih_clk = { + __INIT_CLK_DEBUG(ckih_clk) .get_rate = get_high_reference_clock_rate, }; static struct clk osc_clk = { + __INIT_CLK_DEBUG(osc_clk) .get_rate = get_oscillator_reference_clock_rate, }; @@ -677,6 +686,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate) #define DEF_PLL(name) \ static struct clk name = { \ + __INIT_CLK_DEBUG(name) \ .enable = pll_enable, \ .disable = pll_disable, \ .get_rate = name##_get_rate, \ @@ -796,6 +806,7 @@ static void pfd_disable(struct clk *clk) #define DEF_PFD(name, er, es, p) \ static struct clk name = { \ + __INIT_CLK_DEBUG(name) \ .enable_reg = er, \ .enable_shift = es, \ .enable = pfd_enable, \ @@ -820,6 +831,7 @@ static unsigned long pll2_200m_get_rate(struct clk *clk) } static struct clk pll2_200m = { + __INIT_CLK_DEBUG(pll2_200m) .parent = &pll2_pfd_400m, .get_rate = pll2_200m_get_rate, }; @@ -830,6 +842,7 @@ static unsigned long pll3_120m_get_rate(struct clk *clk) } static struct clk pll3_120m = { + __INIT_CLK_DEBUG(pll3_120m) .parent = &pll3_usb_otg, .get_rate = pll3_120m_get_rate, }; @@ -840,6 +853,7 @@ static unsigned long pll3_80m_get_rate(struct clk *clk) } static struct clk pll3_80m = { + __INIT_CLK_DEBUG(pll3_80m) .parent = &pll3_usb_otg, .get_rate = pll3_80m_get_rate, }; @@ -850,6 +864,7 @@ static unsigned long pll3_60m_get_rate(struct clk *clk) } static struct clk pll3_60m = { + __INIT_CLK_DEBUG(pll3_60m) .parent = &pll3_usb_otg, .get_rate = pll3_60m_get_rate, }; @@ -877,6 +892,7 @@ static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent) } static struct clk pll1_sw_clk = { + __INIT_CLK_DEBUG(pll1_sw_clk) .parent = &pll1_sys, .set_parent = pll1_sw_clk_set_parent, }; @@ -1696,6 +1712,7 @@ static int _clk_set_parent(struct clk *clk, struct clk *parent) #define DEF_NG_CLK(name, p) \ static struct clk name = { \ + __INIT_CLK_DEBUG(name) \ .get_rate = _clk_get_rate, \ .set_rate = _clk_set_rate, \ .round_rate = _clk_round_rate, \ @@ -1723,6 +1740,7 @@ DEF_NG_CLK(asrc_serial_clk, &pll3_usb_otg); #define DEF_CLK(name, er, es, p, s) \ static struct clk name = { \ + __INIT_CLK_DEBUG(name) \ .enable_reg = er, \ .enable_shift = es, \ .enable = _clk_enable, \ @@ -1825,6 +1843,7 @@ static void pcie_clk_disable(struct clk *clk) } static struct clk pcie_clk = { + __INIT_CLK_DEBUG(pcie_clk) .enable_reg = CCGR4, .enable_shift = CG0, .enable = pcie_clk_enable, @@ -1857,6 +1876,7 @@ static void sata_clk_disable(struct clk *clk) } static struct clk sata_clk = { + __INIT_CLK_DEBUG(sata_clk) .enable_reg = CCGR5, .enable_shift = CG2, .enable = sata_clk_enable, @@ -1976,8 +1996,10 @@ int __init mx6q_clocks_init(void) oscillator_reference = rate; } - for (i = 0; i < ARRAY_SIZE(lookups); i++) + for (i = 0; i < ARRAY_SIZE(lookups); i++) { clkdev_add(&lookups[i]); + clk_debug_register(lookups[i].clk); + } /* only keep necessary clocks on */ writel_relaxed(0x3 << CG0 | 0x3 << CG1 | 0x3 << CG2, CCGR0);