From patchwork Thu Dec 15 15:53:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 5773 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C505423E0E for ; Thu, 15 Dec 2011 15:54:38 +0000 (UTC) Received: from mail-lpp01m010-f52.google.com (mail-lpp01m010-f52.google.com [209.85.215.52]) by fiordland.canonical.com (Postfix) with ESMTP id A317DA180F3 for ; Thu, 15 Dec 2011 15:54:38 +0000 (UTC) Received: by mail-lpp01m010-f52.google.com with SMTP id j13so1382271lah.11 for ; Thu, 15 Dec 2011 07:54:38 -0800 (PST) Received: by 10.205.127.12 with SMTP id gy12mr1436158bkc.108.1323964478333; Thu, 15 Dec 2011 07:54:38 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs45394bkc; Thu, 15 Dec 2011 07:54:37 -0800 (PST) Received: by 10.213.8.73 with SMTP id g9mr579640ebg.42.1323964476369; Thu, 15 Dec 2011 07:54:36 -0800 (PST) Received: from mail-fx0-f50.google.com (mail-fx0-f50.google.com [209.85.161.50]) by mx.google.com with ESMTPS id h16si5324883eea.67.2011.12.15.07.54.35 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 15 Dec 2011 07:54:36 -0800 (PST) Received-SPF: neutral (google.com: 209.85.161.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=209.85.161.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.161.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by mail-fx0-f50.google.com with SMTP id q24so2775505faa.37 for ; Thu, 15 Dec 2011 07:54:35 -0800 (PST) Received: by 10.180.19.138 with SMTP id f10mr5976391wie.53.1323964474630; Thu, 15 Dec 2011 07:54:34 -0800 (PST) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id 28sm9930801wby.3.2011.12.15.07.54.32 (version=SSLv3 cipher=OTHER); Thu, 15 Dec 2011 07:54:33 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Anton Vorontsov , Barry Song , Catalin Marinas , Colin Cross , Haojian Zhuang , John Linn , Kukjin Kim , Linus Walleij , linux-omap@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-tegra@vger.kernel.org, Magnus Damm , Paul Mundt , Pawel Moll , Rob Herring , Sascha Hauer , Shawn Guo , Tony Lindgren , Will Deacon Subject: [PATCH v5 5/5] imx6q: Remove unconditional dependency on l2x0 L2 cache support Date: Thu, 15 Dec 2011 15:53:54 +0000 Message-Id: <1323964434-6764-6-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1323964434-6764-1-git-send-email-dave.martin@linaro.org> References: <1323964434-6764-1-git-send-email-dave.martin@linaro.org> The i.MX6 Quad SoC will work without the l2x0 L2 cache controller support built into the kernel, so this patch removes the dependency on CACHE_L2X0. This makes the l2x0 support optional, so that it can be turned off when desired for debugging purposes etc. Since SOC_IMX6Q already depends on ARCH_IMX_V6_V7 and ARCH_IMX_V6_V7 selects MIGHT_HAVE_CACHE_L2X0, there is no need to select that option explicitly from SOC_IMX6Q. Thanks to Shawn Guo for this suggestion. [1] [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074602.html Signed-off-by: Dave Martin --- Changes: v5: Don't select MIGHT_HAVE_CACHE_L2X0 directly from SOC_IMX6Q, but instead select implicitly via ARCH_IMX_V6_V7 (which we expect to be selected by other relevant SoCs). Thanks to Shawn for this suggestion. arch/arm/mach-imx/Kconfig | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 29a3d61..1530678 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -609,7 +609,6 @@ comment "i.MX6 family:" config SOC_IMX6Q bool "i.MX6 Quad support" select ARM_GIC - select CACHE_L2X0 select CPU_V7 select HAVE_ARM_SCU select HAVE_IMX_GPC