From patchwork Thu Dec 15 07:28:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5752 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E9A6623E10 for ; Thu, 15 Dec 2011 07:28:42 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id DFF24A18175 for ; Thu, 15 Dec 2011 07:28:42 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id k10so1764271eaa.11 for ; Wed, 14 Dec 2011 23:28:42 -0800 (PST) Received: by 10.204.156.208 with SMTP id y16mr439555bkw.72.1323934122609; Wed, 14 Dec 2011 23:28:42 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs32690bkc; Wed, 14 Dec 2011 23:28:42 -0800 (PST) Received: by 10.236.192.135 with SMTP id i7mr3403298yhn.13.1323934121600; Wed, 14 Dec 2011 23:28:41 -0800 (PST) Received: from TX2EHSOBE006.bigfish.com (tx2ehsobe003.messaging.microsoft.com. [65.55.88.13]) by mx.google.com with ESMTPS id j35si1005041ann.133.2011.12.14.23.28.41 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Dec 2011 23:28:41 -0800 (PST) Received-SPF: neutral (google.com: 65.55.88.13 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) client-ip=65.55.88.13; Authentication-Results: mx.google.com; spf=neutral (google.com: 65.55.88.13 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) smtp.mail=B20223@freescale.com Received: from mail168-tx2-R.bigfish.com (10.9.14.254) by TX2EHSOBE006.bigfish.com (10.9.40.26) with Microsoft SMTP Server id 14.1.225.23; Thu, 15 Dec 2011 07:28:41 +0000 Received: from mail168-tx2 (localhost [127.0.0.1]) by mail168-tx2-R.bigfish.com (Postfix) with ESMTP id 52A3F3C01B5; Thu, 15 Dec 2011 07:28:45 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail168-tx2 (localhost.localdomain [127.0.0.1]) by mail168-tx2 (MessageSwitch) id 1323934125151165_6559; Thu, 15 Dec 2011 07:28:45 +0000 (UTC) Received: from TX2EHSMHS038.bigfish.com (unknown [10.9.14.248]) by mail168-tx2.bigfish.com (Postfix) with ESMTP id 13FB4580047; Thu, 15 Dec 2011 07:28:45 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS038.bigfish.com (10.9.99.138) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 15 Dec 2011 07:28:40 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.355.3; Thu, 15 Dec 2011 01:28:38 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pBF7SRKk023208; Thu, 15 Dec 2011 01:28:36 -0600 (CST) From: Richard Zhao To: CC: , Richard Zhao , Sascha Hauer , Richard Zhao Subject: [RFC V2 6/8] ARM i.MX: prepare common clk support Date: Thu, 15 Dec 2011 15:28:23 +0800 Message-ID: <1323934105-23255-5-git-send-email-richard.zhao@freescale.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323934105-23255-1-git-send-email-richard.zhao@freescale.com> References: <1323854638-3455-1-git-send-email-richard.zhao@linaro.org> <1323934105-23255-1-git-send-email-richard.zhao@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Add static clock help macros, clock register spinlock. Signed-off-by: Sascha Hauer Signed-off-by: Richard Zhao --- arch/arm/plat-mxc/clock.c | 8 ++++++ arch/arm/plat-mxc/include/mach/clock.h | 42 +++++++++++++++++++++++++++++-- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 2ed3ab1..1973b30 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -41,6 +41,8 @@ #include #include +#ifndef CONFIG_GENERIC_CLK + static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); @@ -199,6 +201,7 @@ struct clk *clk_get_parent(struct clk *clk) return clk->parent; } EXPORT_SYMBOL(clk_get_parent); +#endif /* * Get the resulting clock rate from a PLL register value and the input @@ -244,3 +247,8 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) return ll; } + +#ifdef CONFIG_GENERIC_CLK +DEFINE_SPINLOCK(imx_ccm_lock); +EXPORT_SYMBOL_GPL(imx_ccm_lock); +#endif /* CONFIG_USE_COMMON_STRUCT_CLK */ diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index f62256e..500879b 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h @@ -81,9 +81,13 @@ struct clk_pllv2 { extern struct clk_hw_ops clk_pllv2_ops; -#define DEFINE_CLK_PLLV2(name, _parent, _base) \ - struct clk_pllv2 name = { \ - .parent = (_parent), \ +#define DEFINE_CLK_PLLV2(_name, _parent, _base) \ + struct clk_pllv2 _name = { \ + .clk = { \ + .name = #_name, \ + .ops = &clk_pllv2_ops, \ + .parent = _parent, \ + }, \ .base = (_base), \ } @@ -109,6 +113,38 @@ extern struct clk_hw_ops clk_gate2b_ops; int clk_gate2b_set_val(struct clk *clk, int en, int dis); +extern spinlock_t imx_ccm_lock; + +#define DEFINE_CLK_GATE2B(_name, _parent, _reg, _shift) \ + struct clk_gate2b _name = { \ + .clk = { \ + .name = #_name, \ + .ops = &clk_gate2b_ops, \ + .parent = _parent, \ + }, \ + .reg = (_reg), \ + .shift = (_shift) * 2, \ + .val_en = 0x3, \ + .val_dis = 0x0, \ + .lock = &imx_ccm_lock, \ + } + +#define IMX_DEFINE_CLK_DIVIDER(_name, _parent, _flags, _reg, _shift, _width) \ + DEFINE_CLK_DIVIDER(_name, _parent, _flags, _reg, _shift, _width, \ + &imx_ccm_lock) + +#define IMX_DEFINE_CLK_MUX(_name, _reg, _shift, _width, _clks) \ + DEFINE_CLK_MUX(_name, _reg, _shift, _width, _clks, &imx_ccm_lock) + +#define DEFINE_CLK_FIXED(_name, _rate) \ + struct clk_hw_fixed _name = { \ + .clk = { \ + .name = #_name, \ + .ops = &clk_hw_fixed_ops, \ + }, \ + .fixed_rate = (_rate), \ + } + #endif /* CONFIG_GENERIC_CLK */ #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_MXC_CLOCK_H__ */