From patchwork Tue Dec 13 17:56:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 5642 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3A36023E0C for ; Tue, 13 Dec 2011 17:56:49 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 2F929A1829D for ; Tue, 13 Dec 2011 17:56:49 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id 13so1589962eaa.11 for ; Tue, 13 Dec 2011 09:56:49 -0800 (PST) Received: by 10.204.152.138 with SMTP id g10mr11567515bkw.36.1323799008875; Tue, 13 Dec 2011 09:56:48 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs88578bkc; Tue, 13 Dec 2011 09:56:48 -0800 (PST) Received: by 10.227.206.82 with SMTP id ft18mr17309364wbb.21.1323799007200; Tue, 13 Dec 2011 09:56:47 -0800 (PST) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id gd21si12559505wbb.105.2011.12.13.09.56.47 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 13 Dec 2011 09:56:47 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by mail-ww0-f50.google.com with SMTP id dr11so14211355wgb.31 for ; Tue, 13 Dec 2011 09:56:47 -0800 (PST) Received: by 10.227.205.14 with SMTP id fo14mr17387724wbb.22.1323799005167; Tue, 13 Dec 2011 09:56:45 -0800 (PST) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id dd4sm30779779wib.1.2011.12.13.09.56.43 (version=SSLv3 cipher=OTHER); Tue, 13 Dec 2011 09:56:44 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org Subject: [PATCH v4 4/5] highbank: Unconditionally require l2x0 L2 cache controller support Date: Tue, 13 Dec 2011 17:56:32 +0000 Message-Id: <1323798993-8727-5-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1323798993-8727-1-git-send-email-dave.martin@linaro.org> References: <1323798993-8727-1-git-send-email-dave.martin@linaro.org> If running in the Normal World on a TrustZone-enabled SoC, Linux does not have complete control over the L2 cache controller configuration. The kernel cannot work reliably on such platforms without the l2x0 cache support code built in. This patch unconditionally enables l2x0 support for the Highbank SoC. Thanks to Rob Herring for this suggestion. [1] Signed-off-by: Dave Martin [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074495.html --- arch/arm/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d33eb39..744296d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -340,12 +340,12 @@ config ARCH_HIGHBANK select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 + select CACHE_L2X0 select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 select USE_OF help Support for the Calxeda Highbank SoC based boards.