From patchwork Tue Dec 13 06:25:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5623 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2F2A223E21 for ; Tue, 13 Dec 2011 06:26:12 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 1FC47A182AF for ; Tue, 13 Dec 2011 06:26:12 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id 17so8656841bke.11 for ; Mon, 12 Dec 2011 22:26:12 -0800 (PST) Received: by 10.204.133.213 with SMTP id g21mr8224931bkt.126.1323757571948; Mon, 12 Dec 2011 22:26:11 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs70760bkc; Mon, 12 Dec 2011 22:26:11 -0800 (PST) Received: by 10.229.75.149 with SMTP id y21mr338933qcj.69.1323757570018; Mon, 12 Dec 2011 22:26:10 -0800 (PST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe001.messaging.microsoft.com. [216.32.181.181]) by mx.google.com with ESMTPS id y14si6885293qct.158.2011.12.12.22.26.09 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 12 Dec 2011 22:26:10 -0800 (PST) Received-SPF: neutral (google.com: 216.32.181.181 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) client-ip=216.32.181.181; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.181 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) smtp.mail=richard.zhao@linaro.org Received: from mail10-ch1-R.bigfish.com (10.43.68.252) by CH1EHSOBE015.bigfish.com (10.43.70.65) with Microsoft SMTP Server id 14.1.225.23; Tue, 13 Dec 2011 06:26:05 +0000 Received: from mail10-ch1 (localhost [127.0.0.1]) by mail10-ch1-R.bigfish.com (Postfix) with ESMTP id 0157740198; Tue, 13 Dec 2011 06:26:06 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-SS: 13, X-FB-DOMAIN-IP-MATCH: fail Received: from mail10-ch1 (localhost.localdomain [127.0.0.1]) by mail10-ch1 (MessageSwitch) id 1323757565783467_26237; Tue, 13 Dec 2011 06:26:05 +0000 (UTC) Received: from CH1EHSMHS019.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.245]) by mail10-ch1.bigfish.com (Postfix) with ESMTP id AFE5E580043; Tue, 13 Dec 2011 06:26:05 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS019.bigfish.com (10.43.70.19) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 13 Dec 2011 06:26:05 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.355.3; Tue, 13 Dec 2011 00:26:07 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pBD6PjOP010279; Tue, 13 Dec 2011 00:26:05 -0600 (CST) From: Richard Zhao To: CC: , , , , , Subject: [PATCH V2 7/7] arm/imx6q: add cpufreq support Date: Tue, 13 Dec 2011 14:25:30 +0800 Message-ID: <1323757530-19402-8-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323757530-19402-1-git-send-email-richard.zhao@linaro.org> References: <1323757530-19402-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com use cpu0 node property clock-frequency to check max frequency. Signed-off-by: Richard Zhao --- arch/arm/mach-imx/Kconfig | 1 + arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/cpu_op-imx6q.c | 69 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-imx/cpu_op-imx6q.c diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index fbd414b..21e472f 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -834,6 +834,7 @@ comment "i.MX6 family:" config SOC_IMX6Q bool "i.MX6 Quad support" + select ARCH_HAS_CPUFREQ select ARM_GIC select CACHE_L2X0 select CPU_V7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 9cf630a..2dfe4a7 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -72,7 +72,7 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o -obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o +obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o cpu_op-imx6q.o # i.MX5 based machines obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o diff --git a/arch/arm/mach-imx/cpu_op-imx6q.c b/arch/arm/mach-imx/cpu_op-imx6q.c new file mode 100644 index 0000000..d24e081 --- /dev/null +++ b/arch/arm/mach-imx/cpu_op-imx6q.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +static int arm_max_freq_idx; + +/* operating point(op): 0 - 1GHz; 1 - 800MHz, 3 - 400MHz, 4 - 160MHz */ +static struct cpu_op mx6q_cpu_op[] = { + { + .cpu_rate = 996000000, + .cpu_voltage = 1225000, + }, + { + .cpu_rate = 792000000, + .cpu_voltage = 1100000, + }, + { + .cpu_rate = 396000000, + .cpu_voltage = 950000, + }, + { + .cpu_rate = 198000000, + .cpu_voltage = 850000, + }, +}; + +struct cpu_op *mx6q_get_cpu_op(int *op) +{ + struct device_node *cpu0; + u32 val; + int i; + + cpu0 = of_find_node_by_path("/cpus/cpu@0"); + if (cpu0 && !of_property_read_u32(cpu0, "clock-frequency", &val)) { + for (i = 0; i < ARRAY_SIZE(mx6q_cpu_op); i++) { + if (val >= mx6q_cpu_op[i].cpu_rate) { + arm_max_freq_idx = i; + break; + } + } + } + if (cpu0) + of_node_put(cpu0); + *op = ARRAY_SIZE(mx6q_cpu_op) - arm_max_freq_idx; + return mx6q_cpu_op + arm_max_freq_idx; +} + +static int __init mx6q_cpu_op_init(void) +{ + get_cpu_op = mx6q_get_cpu_op; + return 0; +} + +core_initcall(mx6q_cpu_op_init);