From patchwork Mon Dec 12 09:56:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 5588 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 015C323E33 for ; Mon, 12 Dec 2011 09:57:22 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id E4631A1861C for ; Mon, 12 Dec 2011 09:57:21 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id 17so6969333bke.11 for ; Mon, 12 Dec 2011 01:57:21 -0800 (PST) Received: by 10.205.120.135 with SMTP id fy7mr4462845bkc.54.1323683841699; Mon, 12 Dec 2011 01:57:21 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs42846bkc; Mon, 12 Dec 2011 01:57:21 -0800 (PST) Received: by 10.14.24.35 with SMTP id w35mr2558520eew.224.1323683839861; Mon, 12 Dec 2011 01:57:19 -0800 (PST) Received: from eu1sys200aog120.obsmtp.com (eu1sys200aog120.obsmtp.com. [207.126.144.149]) by mx.google.com with SMTP id c40si527994eec.180.2011.12.12.01.57.08 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 12 Dec 2011 01:57:19 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.149 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.149; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.149 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob120.postini.com ([207.126.147.11]) with SMTP ID DSNKTuXP7VYSGm2xw+6hJ0oTzLxcQkvcUMty@postini.com; Mon, 12 Dec 2011 09:57:19 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3D39CF9; Mon, 12 Dec 2011 09:48:30 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 4C13B8D4; Mon, 12 Dec 2011 09:56:55 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 49BE0A80A1; Mon, 12 Dec 2011 10:56:50 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Mon, 12 Dec 2011 10:56:53 +0100 From: Linus Walleij To: Russell King , Cc: Colin Cross , Thomas Gleixner , Rob Herring , Santosh Shilimkar , Linus Walleij , Russell King Subject: [PATCH 1/4] ARM: smp_twd: modernize clock event registration Date: Mon, 12 Dec 2011 10:56:45 +0100 Message-ID: <1323683805-23830-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij This break-out from Colin Cross' cpufreq-aware TWD patch will just modernize the clock event registration code to use clockevents_config_and_register(). Signed-off-by: Colin Cross Cc: Russell King Acked-by: Thomas Gleixner Acked-by: Rob Herring Acked-by: Santosh Shilimkar [Broke out of larger SMP TWD patch] Signed-off-by: Linus Walleij --- arch/arm/kernel/smp_twd.c | 8 ++------ 1 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index a8a6682..f057561 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -173,15 +173,11 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) clk->rating = 350; clk->set_mode = twd_set_mode; clk->set_next_event = twd_set_next_event; - clk->shift = 20; - clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift); - clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); - clk->min_delta_ns = clockevent_delta2ns(0xf, clk); this_cpu_clk = __this_cpu_ptr(twd_evt); *this_cpu_clk = clk; - clockevents_register_device(clk); - + clockevents_config_and_register(clk, twd_timer_rate, + 0xf, 0xffffffff); enable_percpu_irq(clk->irq, 0); }