From patchwork Thu Dec 8 01:28:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 5536 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2547423E0C for ; Thu, 8 Dec 2011 01:29:02 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 13729A1865C for ; Thu, 8 Dec 2011 01:29:02 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id 17so1574286bke.11 for ; Wed, 07 Dec 2011 17:29:02 -0800 (PST) Received: by 10.205.127.12 with SMTP id gy12mr492202bkc.108.1323307741771; Wed, 07 Dec 2011 17:29:01 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs84026bkc; Wed, 7 Dec 2011 17:29:01 -0800 (PST) Received: by 10.68.17.10 with SMTP id k10mr10392936pbd.79.1323307739534; Wed, 07 Dec 2011 17:28:59 -0800 (PST) Received: from VA3EHSOBE005.bigfish.com (va3ehsobe005.messaging.microsoft.com. [216.32.180.31]) by mx.google.com with ESMTPS id m3si5602646pbs.24.2011.12.07.17.28.58 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Dec 2011 17:28:59 -0800 (PST) Received-SPF: neutral (google.com: 216.32.180.31 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) client-ip=216.32.180.31; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.180.31 is neither permitted nor denied by best guess record for domain of richard.zhao@linaro.org) smtp.mail=richard.zhao@linaro.org Received: from mail13-va3-R.bigfish.com (10.7.14.238) by VA3EHSOBE005.bigfish.com (10.7.40.25) with Microsoft SMTP Server id 14.1.225.23; Thu, 8 Dec 2011 01:28:57 +0000 Received: from mail13-va3 (localhost [127.0.0.1]) by mail13-va3-R.bigfish.com (Postfix) with ESMTP id C29B96801BC; Thu, 8 Dec 2011 01:28:57 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail13-va3 (localhost.localdomain [127.0.0.1]) by mail13-va3 (MessageSwitch) id 1323307737308526_19282; Thu, 8 Dec 2011 01:28:57 +0000 (UTC) Received: from VA3EHSMHS003.bigfish.com (unknown [10.7.14.246]) by mail13-va3.bigfish.com (Postfix) with ESMTP id 442D26C0046; Thu, 8 Dec 2011 01:28:57 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS003.bigfish.com (10.7.99.13) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 8 Dec 2011 01:28:41 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.339.2; Wed, 7 Dec 2011 19:28:52 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pB81SiGr025900; Wed, 7 Dec 2011 19:28:50 -0600 (CST) From: Richard Zhao To: CC: , , , Subject: [PATCH V2 2/2] ARM: mx51/53: add round_rate for esdhc clocks Date: Thu, 8 Dec 2011 09:28:34 +0800 Message-ID: <1323307714-21290-3-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1323307714-21290-1-git-send-email-richard.zhao@linaro.org> References: <1323307714-21290-1-git-send-email-richard.zhao@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Signed-off-by: Richard Zhao --- arch/arm/mach-imx/clock-mx51-mx53.c | 42 ++++++++++++++++++++-------------- 1 files changed, 25 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-imx/clock-mx51-mx53.c b/arch/arm/mach-imx/clock-mx51-mx53.c index 716533b..7df85ba 100644 --- a/arch/arm/mach-imx/clock-mx51-mx53.c +++ b/arch/arm/mach-imx/clock-mx51-mx53.c @@ -1013,20 +1013,6 @@ static struct clk mipi_hsp_clk = { .secondary = s, \ } -#define DEFINE_CLOCK_ESDHC(name, i, er, es, pfx, p, s) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = pfx##_get_rate, \ - .set_rate = pfx##_set_rate, \ - .set_parent = pfx##_set_parent, \ - .enable = _clk_ccgr_enable, \ - .disable = _clk_ccgr_disable, \ - .parent = p, \ - .secondary = s, \ - } - #define CLK_GET_RATE(name, nr, bitsname) \ static unsigned long clk_##name##_get_rate(struct clk *clk) \ { \ @@ -1088,6 +1074,25 @@ static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \ return 0; \ } +#define CLK_ROUND_RATE(name , nr, bitsname) \ +static unsigned long clk_##name##_round_rate(struct clk *clk, \ + unsigned long rate) \ +{ \ + u32 div, parent_rate; \ + u32 pre = 0, post = 0; \ + \ + parent_rate = clk_get_rate(clk->parent); \ + div = DIV_ROUND_UP(parent_rate, rate); \ + \ + __calc_pre_post_dividers(div, &pre, &post, \ + (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \ + MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \ + (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \ + MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1); \ + \ + return parent_rate / pre / post; \ +} + /* UART */ CLK_GET_RATE(uart, 1, UART) CLK_SET_PARENT(uart, 1, UART) @@ -1157,11 +1162,13 @@ static struct clk ecspi_main_clk = { CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1) CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1) CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1) +CLK_ROUND_RATE(esdhc1, 1, ESDHC1_MSHC1) /* mx51 specific */ CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2) CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2) CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2) +CLK_ROUND_RATE(esdhc2, 1, ESDHC2_MSHC2) static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) { @@ -1215,6 +1222,7 @@ static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent) CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53) CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53) CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53) +CLK_ROUND_RATE(esdhc3_mx53, 1, ESDHC3_MX53) static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent) { @@ -1342,7 +1350,7 @@ DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET, /* eSDHC */ DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET, NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); -DEFINE_CLOCK_ESDHC(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET, +DEFINE_CLOCK_CCGR(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET, clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk); DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); @@ -1352,7 +1360,7 @@ DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET, NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); /* mx51 specific */ -DEFINE_CLOCK_ESDHC(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, +DEFINE_CLOCK_CCGR(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); static struct clk esdhc3_clk = { @@ -1388,7 +1396,7 @@ static struct clk esdhc2_mx53_clk = { .secondary = &esdhc3_ipg_clk, }; -DEFINE_CLOCK_ESDHC(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET, +DEFINE_CLOCK_CCGR(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET, clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk); static struct clk esdhc4_mx53_clk = {