From patchwork Wed Dec 7 17:24:21 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 5532 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D382223E04 for ; Wed, 7 Dec 2011 17:24:32 +0000 (UTC) Received: from mail-ee0-f52.google.com (mail-ee0-f52.google.com [74.125.83.52]) by fiordland.canonical.com (Postfix) with ESMTP id C1B62A18D1C for ; Wed, 7 Dec 2011 17:24:32 +0000 (UTC) Received: by eekc14 with SMTP id c14so867351eek.11 for ; Wed, 07 Dec 2011 09:24:32 -0800 (PST) Received: by 10.14.17.211 with SMTP id j59mr3959312eej.138.1323278672447; Wed, 07 Dec 2011 09:24:32 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs75788bkc; Wed, 7 Dec 2011 09:24:30 -0800 (PST) Received: by 10.14.2.134 with SMTP id 6mr3744996eef.8.1323278669294; Wed, 07 Dec 2011 09:24:29 -0800 (PST) Received: from mail-bw0-f50.google.com (mail-bw0-f50.google.com [209.85.214.50]) by mx.google.com with ESMTPS id h16si1315721eea.175.2011.12.07.09.24.29 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Dec 2011 09:24:29 -0800 (PST) Received-SPF: neutral (google.com: 209.85.214.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=209.85.214.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by bkcik5 with SMTP id ik5so819339bkc.37 for ; Wed, 07 Dec 2011 09:24:29 -0800 (PST) Received: by 10.180.4.102 with SMTP id j6mr25325861wij.38.1323278668734; Wed, 07 Dec 2011 09:24:28 -0800 (PST) Received: from localhost.localdomain ([213.123.120.124]) by mx.google.com with ESMTPS id bs13sm3846182wib.21.2011.12.07.09.24.26 (version=SSLv3 cipher=OTHER); Wed, 07 Dec 2011 09:24:27 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Bi Junxiao , Rabin Vincent , Tixy , Leif Lindholm Subject: [PATCH] ARM: Add generic instruction opcode manipulation helpers Date: Wed, 7 Dec 2011 17:24:21 +0000 Message-Id: <1323278661-29195-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 This patch adds some endianness-agnostic helpers to convert machine instructions between canonical integer form and in-memory representation. A canonical integer form for representing instructions is also formalised here. Signed-off-by: Dave Martin Acked-by: Nicolas Pitre --- Changes since RFC: v1: Delete the unnecessarily heavyweight instruction read/write macros. After discussion, it seems that these weren't likely to be very useful. arch/arm/include/asm/opcodes.h | 70 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/opcodes.h diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h new file mode 100644 index 0000000..bb70898 --- /dev/null +++ b/arch/arm/include/asm/opcodes.h @@ -0,0 +1,70 @@ +/* + * arch/arm/include/asm/opcodes.h + * + * Copyright (C) 2011 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARM_OPCODES_H +#define __ARM_OPCODES_H + +#include +#include + +typedef u32 arm_opcode_t; + +/* + * Canonical instruction representation (arm_opcode_t): + * + * ARM: 0xKKLLMMNN + * Thumb 16-bit: 0x0000KKLL, where KK < 0xE8 + * Thumb 32-bit: 0xKKLLMMNN, where KK >= 0xE8 + * + * There is no way to distinguish an ARM instruction in canonical representation + * from a Thumb instruction (just as these cannot be distinguished in memory). + * Where this distinction is important, it needs to be tracked separately. + * + * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not + * represent any valid Thumb-2 instruction. For this range, + * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false. + */ + +#ifdef CONFIG_CPU_ENDIAN_BE8 +#define __opcode_to_mem_arm(x) swab32(x) +#define __opcode_to_mem_thumb16(x) swab16(x) +#define __opcode_to_mem_thumb32(x) swahb32(x) +#else +#define __opcode_to_mem_arm(x) (x) ((u32)(x)) +#define __opcode_to_mem_thumb16(x) ((u16)(x)) +#define __opcode_to_mem_thumb32(x) swahw32(x) +#endif + +#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x) +#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x) +#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x) + +/* Operations specific to Thumb opcodes */ + +/* Instruction size checks: */ +#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL) +#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL) + +/* Operations to construct or split 32-bit Thumb instructions: */ +#define __opcode_thumb32_first(x) ((u16)((thumb_opcode) >> 16)) +#define __opcode_thumb32_second(x) ((u16)(thumb_opcode)) +#define __opcode_thumb32_compose(first, second) \ + (((u32)(u16)(first) << 16) | (u32)(u16)(second)) + +#endif /* ! __ARM_OPCODES_H */