From patchwork Tue Nov 29 17:12:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 5383 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 35EA823FFB for ; Tue, 29 Nov 2011 17:12:52 +0000 (UTC) Received: from mail-lpp01m010-f52.google.com (mail-lpp01m010-f52.google.com [209.85.215.52]) by fiordland.canonical.com (Postfix) with ESMTP id 1B341A1809D for ; Tue, 29 Nov 2011 17:12:52 +0000 (UTC) Received: by laah2 with SMTP id h2so1447028laa.11 for ; Tue, 29 Nov 2011 09:12:51 -0800 (PST) Received: by 10.152.110.130 with SMTP id ia2mr10922090lab.26.1322586771723; Tue, 29 Nov 2011 09:12:51 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.41.198 with SMTP id h6cs11825lal; Tue, 29 Nov 2011 09:12:51 -0800 (PST) Received: by 10.204.136.214 with SMTP id s22mr18723627bkt.136.1322586769523; Tue, 29 Nov 2011 09:12:49 -0800 (PST) Received: from mail-fx0-f50.google.com (mail-fx0-f50.google.com [209.85.161.50]) by mx.google.com with ESMTPS id w4si29382933bkd.90.2011.11.29.09.12.49 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 29 Nov 2011 09:12:49 -0800 (PST) Received-SPF: neutral (google.com: 209.85.161.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=209.85.161.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.161.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by faao26 with SMTP id o26so1168824faa.37 for ; Tue, 29 Nov 2011 09:12:49 -0800 (PST) Received: by 10.181.13.82 with SMTP id ew18mr50711584wid.16.1322586768869; Tue, 29 Nov 2011 09:12:48 -0800 (PST) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id z35sm16347081wbm.12.2011.11.29.09.12.47 (version=SSLv3 cipher=OTHER); Tue, 29 Nov 2011 09:12:48 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Will Deacon , Catalin Marinas Subject: [PATCH] ARM: errata: Remove SMP dependency for erratum 751472 Date: Tue, 29 Nov 2011 17:12:43 +0000 Message-Id: <1322586763-12791-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 Activation conditions for a workaround should not be encoded in the workaround's direct dependencies if this makes otherwise reasonable configuration choices impossible. This patches uses the SMP/UP patching facilities instead to compile out the workaround if the configuration means that it is definitely not needed. This means that configs for buggy silicon can simply select ARM_ERRATA_751472, without preventing a UP kernel from being built or duplicatiing knowledge about when to activate the workaround. This seems the correct why to do things, because the erratum is a property of the silicon, irrespective of what the kernel config happens to be. Signed-off-by: Dave Martin --- arch/arm/Kconfig | 2 +- arch/arm/mm/proc-v7.S | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 44789ef..e5bbb2f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1281,7 +1281,7 @@ config ARM_ERRATA_743622 config ARM_ERRATA_751472 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" - depends on CPU_V7 && SMP + depends on CPU_V7 help This option enables the workaround for the 751472 Cortex-A9 (prior to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 2c559ac..9b06d0b 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -364,10 +364,12 @@ __v7_setup: mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif #ifdef CONFIG_ARM_ERRATA_751472 - cmp r6, #0x30 @ present prior to r3p0 + ALT_UP_B(1f) + ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register orrlt r10, r10, #1 << 11 @ set bit #11 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register +1: #endif 3: mov r10, #0