From patchwork Wed Nov 9 13:00:02 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 4973 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 46E8523E13 for ; Wed, 9 Nov 2011 13:00:27 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 2C280A1810B for ; Wed, 9 Nov 2011 13:00:27 +0000 (UTC) Received: by faan26 with SMTP id n26so2281546faa.11 for ; Wed, 09 Nov 2011 05:00:27 -0800 (PST) Received: by 10.152.102.138 with SMTP id fo10mr1458265lab.44.1320843626788; Wed, 09 Nov 2011 05:00:26 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.10.72 with SMTP id g8cs167543lab; Wed, 9 Nov 2011 05:00:25 -0800 (PST) Received: by 10.213.9.77 with SMTP id k13mr188052ebk.124.1320843623654; Wed, 09 Nov 2011 05:00:23 -0800 (PST) Received: from eu1sys200aog106.obsmtp.com (eu1sys200aog106.obsmtp.com. [207.126.144.121]) by mx.google.com with SMTP id v41si1192559eef.81.2011.11.09.05.00.18 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 09 Nov 2011 05:00:23 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.121 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.121; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.121 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob106.postini.com ([207.126.147.11]) with SMTP ID DSNKTrp5X5XZxxhPUVLBOszAgzd8oC0IShCE@postini.com; Wed, 09 Nov 2011 13:00:23 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 2D705CE; Wed, 9 Nov 2011 12:51:45 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 4DE309E6; Wed, 9 Nov 2011 13:00:12 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 09F0424C2F2; Wed, 9 Nov 2011 14:00:05 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 9 Nov 2011 14:00:11 +0100 From: Linus Walleij To: Cc: Rabin Vincent , Will Deacon , Linus Walleij Subject: [PATCH] ARM: hw_breakpoint: don't fault when debug is not powered Date: Wed, 9 Nov 2011 14:00:02 +0100 Message-ID: <1320843602-12278-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Rabin Vincent If the debug logic is not powered, the processor can unfortunately raise an undefined instruction exception on the instruction that we use to check if the debug logic is powered up or not. Handle this with an undef hook, so that the kernel doesn't crash on boot on such setups. Cc: Will Deacon Signed-off-by: Rabin Vincent Signed-off-by: Linus Walleij --- arch/arm/kernel/hw_breakpoint.c | 25 +++++++++++++++++++++++++ 1 files changed, 25 insertions(+), 0 deletions(-) diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 814a52a9..f46137c 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -854,6 +854,25 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, return ret; } +static int hw_breakpoint_undef(struct pt_regs *regs, unsigned int instr) +{ + int reg = (instr >> 12) & 15; + + /* Fake sticky power-down cleared */ + regs->uregs[reg] = 0; + regs->ARM_pc += 4; + + return 0; +} + +static struct undef_hook hw_breakpoint_hook = { + .instr_mask = 0xffff0fff, + .instr_val = 0xee110e95, + .cpsr_mask = MODE_MASK, + .cpsr_val = SVC_MODE, + .fn = hw_breakpoint_undef, +}; + /* * One-time initialisation. */ @@ -900,6 +919,10 @@ static void reset_ctrl_regs(void *unused) /* * Ensure sticky power-down is clear (i.e. debug logic is * powered up). + * + * This could raise an undefined instruction exception. If it + * does, it is fixed up with an undef hook which constructs + * a fake value with the sticky power-down bit cleared. */ asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power)); if ((dbg_power & 0x1) == 0) @@ -980,6 +1003,8 @@ static int __init arch_hw_breakpoint_init(void) core_num_brps = get_num_brps(); core_num_wrps = get_num_wrps(); + register_undef_hook(&hw_breakpoint_hook); + /* * We need to tread carefully here because DBGSWENABLE may be * driven low on this core and there isn't an architected way to