From patchwork Mon Nov 7 03:02:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 4945 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B168423FCD for ; Mon, 7 Nov 2011 03:03:41 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id A3E53A1851E for ; Mon, 7 Nov 2011 03:03:41 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id n26so6741218faa.11 for ; Sun, 06 Nov 2011 19:03:41 -0800 (PST) Received: by 10.152.105.67 with SMTP id gk3mr5621532lab.48.1320635021500; Sun, 06 Nov 2011 19:03:41 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.14.103 with SMTP id o7cs43458lac; Sun, 6 Nov 2011 19:03:41 -0800 (PST) Received: by 10.216.136.13 with SMTP id v13mr6426670wei.101.1320635013399; Sun, 06 Nov 2011 19:03:33 -0800 (PST) Received: from DB3EHSOBE003.bigfish.com (mail-db3.bigfish.com. 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IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-SS: 0,13, X-FB-DOMAIN-IP-MATCH: fail Received: from mail35-db3 (localhost.localdomain [127.0.0.1]) by mail35-db3 (MessageSwitch) id 1320634999278724_17621; Mon, 7 Nov 2011 03:03:19 +0000 (UTC) Received: from DB3EHSMHS007.bigfish.com (unknown [10.3.81.246]) by mail35-db3.bigfish.com (Postfix) with ESMTP id 357BCC38052; Mon, 7 Nov 2011 03:03:19 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS007.bigfish.com (10.3.87.107) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 7 Nov 2011 03:03:06 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.339.2; Sun, 6 Nov 2011 21:03:25 -0600 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pA733Mx4002308; Sun, 6 Nov 2011 21:03:23 -0600 (CST) From: Richard Zhao To: CC: , , , Richard Zhao Subject: [PATCH 1/2] ARM: mx51/53: correct misuse of _clk_max_enable and _clk_max_disable Date: Mon, 7 Nov 2011 11:02:15 +0800 Message-ID: <1320634936-7898-1-git-send-email-richard.zhao@linaro.org> X-Mailer: git-send-email 1.7.5.4 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Signed-off-by: Richard Zhao --- arch/arm/mach-mx5/clock-mx51-mx53.c | 70 +++++++++++++++++++--------------- 1 files changed, 39 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index a3ca4ce..507d24c 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1013,20 +1013,6 @@ static struct clk mipi_hsp_clk = { .secondary = s, \ } -#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = pfx##_get_rate, \ - .set_rate = pfx##_set_rate, \ - .set_parent = pfx##_set_parent, \ - .enable = _clk_max_enable, \ - .disable = _clk_max_disable, \ - .parent = p, \ - .secondary = s, \ - } - #define CLK_GET_RATE(name, nr, bitsname) \ static unsigned long clk_##name##_get_rate(struct clk *clk) \ { \ @@ -1088,6 +1074,25 @@ static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \ return 0; \ } +#define CLK_ROUND_RATE(name , nr, bitsname) \ +static unsigned long clk_##name##_round_rate(struct clk *clk, \ + unsigned long rate) \ +{ \ + u32 div, parent_rate; \ + u32 pre = 0, post = 0; \ + \ + parent_rate = clk_get_rate(clk->parent); \ + div = DIV_ROUND_UP(parent_rate, rate); \ + \ + __calc_pre_post_dividers(div, &pre, &post, \ + (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \ + MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \ + (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \ + MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1); \ + \ + return parent_rate / pre / post; \ +} + /* UART */ CLK_GET_RATE(uart, 1, UART) CLK_SET_PARENT(uart, 1, UART) @@ -1157,11 +1162,13 @@ static struct clk ecspi_main_clk = { CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1) CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1) CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1) +CLK_ROUND_RATE(esdhc1, 1, ESDHC1_MSHC1) /* mx51 specific */ CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2) CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2) CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2) +CLK_ROUND_RATE(esdhc2, 1, ESDHC2_MSHC2) static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) { @@ -1215,6 +1222,7 @@ static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent) CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53) CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53) CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53) +CLK_ROUND_RATE(esdhc3_mx53, 1, ESDHC3_MX53) static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent) { @@ -1341,18 +1349,18 @@ DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET, /* eSDHC */ DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); -DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET, + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); +DEFINE_CLOCK_CCGR(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET, clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk); DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); + NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable, &ipg_clk, NULL); /* mx51 specific */ -DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, +DEFINE_CLOCK_CCGR(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); static struct clk esdhc3_clk = { @@ -1361,8 +1369,8 @@ static struct clk esdhc3_clk = { .set_parent = clk_esdhc3_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, .secondary = &esdhc3_ipg_clk, }; static struct clk esdhc4_clk = { @@ -1371,8 +1379,8 @@ static struct clk esdhc4_clk = { .set_parent = clk_esdhc4_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, .secondary = &esdhc4_ipg_clk, }; @@ -1383,12 +1391,12 @@ static struct clk esdhc2_mx53_clk = { .set_parent = clk_esdhc2_mx53_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, .secondary = &esdhc3_ipg_clk, }; -DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET, +DEFINE_CLOCK_CCGR(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET, clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk); static struct clk esdhc4_mx53_clk = { @@ -1397,17 +1405,17 @@ static struct clk esdhc4_mx53_clk = { .set_parent = clk_esdhc4_mx53_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable, .secondary = &esdhc4_ipg_clk, }; static struct clk sata_clk = { .parent = &ipg_clk, - .enable = _clk_max_enable, + .enable = _clk_ccgr_enable, .enable_reg = MXC_CCM_CCGR4, .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, - .disable = _clk_max_disable, + .disable = _clk_ccgr_disable, }; static struct clk ahci_phy_clk = {