From patchwork Tue Oct 4 10:38:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Girish K S X-Patchwork-Id: 4507 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D9CF223F56 for ; Tue, 4 Oct 2011 10:37:35 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id C3965A18115 for ; Tue, 4 Oct 2011 10:37:35 +0000 (UTC) Received: by bke5 with SMTP id 5so612205bke.11 for ; Tue, 04 Oct 2011 03:37:35 -0700 (PDT) Received: by 10.223.57.17 with SMTP id a17mr1529533fah.65.1317724655338; Tue, 04 Oct 2011 03:37:35 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.23.170 with SMTP id n10cs46055laf; Tue, 4 Oct 2011 03:37:35 -0700 (PDT) Received: by 10.68.19.40 with SMTP id b8mr8958444pbe.17.1317724653788; Tue, 04 Oct 2011 03:37:33 -0700 (PDT) Received: from mail-pz0-f42.google.com (mail-pz0-f42.google.com [209.85.210.42]) by mx.google.com with ESMTPS id s8si9942391pba.75.2011.10.04.03.37.32 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 04 Oct 2011 03:37:33 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.42 is neither permitted nor denied by best guess record for domain of girish.shivananjappa@linaro.org) client-ip=209.85.210.42; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.42 is neither permitted nor denied by best guess record for domain of girish.shivananjappa@linaro.org) smtp.mail=girish.shivananjappa@linaro.org Received: by pzk1 with SMTP id 1so969909pzk.1 for ; Tue, 04 Oct 2011 03:37:32 -0700 (PDT) Received: by 10.68.27.102 with SMTP id s6mr8581802pbg.43.1317724652469; Tue, 04 Oct 2011 03:37:32 -0700 (PDT) Received: from girishks ([115.113.119.130]) by mx.google.com with ESMTPS id z1sm63660139pbl.5.2011.10.04.03.37.28 (version=SSLv3 cipher=OTHER); Tue, 04 Oct 2011 03:37:31 -0700 (PDT) From: Girish K S To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, linux-samsung-soc@vger.kernel.org, hyok.choi@samsung.com, rmk+kernel@arm.linux.org.uk, Girish K S Subject: [PATCH] arm: mm: Fix infinite looping issue Date: Tue, 4 Oct 2011 16:08:04 +0530 Message-Id: <1317724684-29115-1-git-send-email-girish.shivananjappa@linaro.org> X-Mailer: git-send-email 1.7.1 This patch fixes the problem of infinite looping while booting. The bne instruction expects the z flag to be set to break the loop. The (mov r1, r1, lsr #1) doesn't behave in the expected way. If replaced with the movs instruction then the execution will exit the loop. Signed-off-by: Girish K S --- arch/arm/mm/proc-arm740.S | 4 ++-- arch/arm/mm/proc-arm940.S | 4 ++-- arch/arm/mm/proc-arm946.S | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index 4506be3..9284f10 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S @@ -77,7 +77,7 @@ __arm740_setup: ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) mov r2, #10 @ 11 is the minimum (4KB) 1: add r2, r2, #1 @ area size *= 2 - mov r1, r1, lsr #1 + movs r1, r1, lsr #1 @ set zero bit if r1=0 bne 1b @ count not zero r-shift orr r0, r0, r2, lsl #1 @ the area register value orr r0, r0, #1 @ set enable bit @@ -87,7 +87,7 @@ __arm740_setup: ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB) mov r2, #10 @ 11 is the minimum (4KB) 1: add r2, r2, #1 @ area size *= 2 - mov r1, r1, lsr #1 + movs r1, r1, lsr #1 @ set zero bit if r1=0 bne 1b @ count not zero r-shift orr r0, r0, r2, lsl #1 @ the area register value orr r0, r0, #1 @ set enable bit diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index ac750d5..e639034 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -296,7 +296,7 @@ __arm940_setup: ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) mov r2, #10 @ 11 is the minimum (4KB) 1: add r2, r2, #1 @ area size *= 2 - mov r1, r1, lsr #1 + movs r1, r1, lsr #1 @ set zero bit if r1=0 bne 1b @ count not zero r-shift orr r0, r0, r2, lsl #1 @ the area register value orr r0, r0, #1 @ set enable bit @@ -307,7 +307,7 @@ __arm940_setup: ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB) mov r2, #10 @ 11 is the minimum (4KB) 1: add r2, r2, #1 @ area size *= 2 - mov r1, r1, lsr #1 + movs r1, r1, lsr #1 @ set zero bit if r1=0 bne 1b @ count not zero r-shift orr r0, r0, r2, lsl #1 @ the area register value orr r0, r0, #1 @ set enable bit diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 683af3a..731388a 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -341,7 +341,7 @@ __arm946_setup: ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) mov r2, #10 @ 11 is the minimum (4KB) 1: add r2, r2, #1 @ area size *= 2 - mov r1, r1, lsr #1 + movs r1, r1, lsr #1 @ set zero bit if r1=0 bne 1b @ count not zero r-shift orr r0, r0, r2, lsl #1 @ the region register value orr r0, r0, #1 @ set enable bit @@ -351,7 +351,7 @@ __arm946_setup: ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB) mov r2, #10 @ 11 is the minimum (4KB) 1: add r2, r2, #1 @ area size *= 2 - mov r1, r1, lsr #1 + movs r1, r1, lsr #1 @ set zero bit if r1=0 bne 1b @ count not zero r-shift orr r0, r0, r2, lsl #1 @ the region register value orr r0, r0, #1 @ set enable bit