From patchwork Mon Oct 3 02:57:01 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 4469 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 278D823EF5 for ; Mon, 3 Oct 2011 02:54:23 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 165F0A1867A for ; Mon, 3 Oct 2011 02:54:23 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id 5so6475680bke.11 for ; Sun, 02 Oct 2011 19:54:23 -0700 (PDT) Received: by 10.223.55.136 with SMTP id u8mr20155458fag.46.1317610461559; Sun, 02 Oct 2011 19:54:21 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.23.170 with SMTP id n10cs628laf; Sun, 2 Oct 2011 19:54:21 -0700 (PDT) Received: by 10.236.156.67 with SMTP id l43mr67167681yhk.10.1317610460356; Sun, 02 Oct 2011 19:54:20 -0700 (PDT) Received: from mail-yw0-f50.google.com (mail-yw0-f50.google.com [209.85.213.50]) by mx.google.com with ESMTPS id y7si11739463yhl.105.2011.10.02.19.54.19 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 02 Oct 2011 19:54:20 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.213.50 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) client-ip=209.85.213.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.213.50 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) smtp.mail=shawn.guo@linaro.org Received: by mail-yw0-f50.google.com with SMTP id 13so3644543ywm.37 for ; Sun, 02 Oct 2011 19:54:19 -0700 (PDT) Received: by 10.68.20.135 with SMTP id n7mr76445352pbe.125.1317610458111; Sun, 02 Oct 2011 19:54:18 -0700 (PDT) Received: from localhost.localdomain ([117.80.113.243]) by mx.google.com with ESMTPS id lh6sm48857459pbb.12.2011.10.02.19.54.13 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 02 Oct 2011 19:54:17 -0700 (PDT) From: Shawn Guo To: Arnd Bergmann , Sascha Hauer Cc: linux-arm-kernel@lists.infradead.org, patches@linaro.org, Shawn Guo Subject: [PATCH v5 3/8] arm/imx: add gic_handle_irq function Date: Mon, 3 Oct 2011 10:57:01 +0800 Message-Id: <1317610626-24357-4-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org> References: <1317610626-24357-1-git-send-email-shawn.guo@linaro.org> This is a plain translation of assembly gic irq handler to C function for CONFIG_MULTI_IRQ_HANDLER support on imx family. Signed-off-by: Shawn Guo --- arch/arm/plat-mxc/Makefile | 2 +- arch/arm/plat-mxc/gic.c | 47 ++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/common.h | 2 + arch/arm/plat-mxc/include/mach/entry-macro.S | 6 +++ 4 files changed, 56 insertions(+), 1 deletions(-) create mode 100644 arch/arm/plat-mxc/gic.c diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index d53c35f..b9f0f5f 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -5,7 +5,7 @@ # Common support obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o -# MX51 uses the TZIC interrupt controller, older platforms use AVIC +obj-$(CONFIG_ARM_GIC) += gic.o obj-$(CONFIG_MXC_TZIC) += tzic.o obj-$(CONFIG_MXC_AVIC) += avic.o diff --git a/arch/arm/plat-mxc/gic.c b/arch/arm/plat-mxc/gic.c new file mode 100644 index 0000000..aed9d70 --- /dev/null +++ b/arch/arm/plat-mxc/gic.c @@ -0,0 +1,47 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#ifdef CONFIG_SMP +#include +#endif + +asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) +{ + u32 irqstat, irqnr; + + do { + irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK); + irqnr = irqstat & 0x3ff; + if (irqnr == 1023) + break; + + if (irqnr > 29 && irqnr < 1021) + handle_IRQ(irqnr, regs); +#ifdef CONFIG_SMP + else if (irqnr < 16) { + writel_relaxed(irqstat, gic_cpu_base_addr + + GIC_CPU_EOI); + handle_IPI(irqnr, regs); + } +#endif +#ifdef CONFIG_LOCAL_TIMERS + else if (irqnr == 29) { + writel_relaxed(irqstat, gic_cpu_base_addr + + GIC_CPU_EOI); + handle_local_timer(regs); + } +#endif + } while (1); +} diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index ace4bb5..c225837 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -86,6 +86,7 @@ extern void imx_print_silicon_rev(const char *cpu, int srev); void avic_handle_irq(struct pt_regs *); void tzic_handle_irq(struct pt_regs *); +void gic_handle_irq(struct pt_regs *); #define imx1_handle_irq avic_handle_irq #define imx21_handle_irq avic_handle_irq @@ -96,5 +97,6 @@ void tzic_handle_irq(struct pt_regs *); #define imx50_handle_irq tzic_handle_irq #define imx51_handle_irq tzic_handle_irq #define imx53_handle_irq tzic_handle_irq +#define imx6q_handle_irq gic_handle_irq #endif diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index 842fbcb..9fe0dfc 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -22,3 +22,9 @@ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp .endm + + .macro test_for_ipi, irqnr, irqstat, base, tmp + .endm + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + .endm