From patchwork Thu Sep 22 13:46:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 4265 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 61AE823EFA for ; Thu, 22 Sep 2011 13:46:54 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 54B35A1810C for ; Thu, 22 Sep 2011 13:46:54 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id 23so3864669fxe.11 for ; Thu, 22 Sep 2011 06:46:54 -0700 (PDT) Received: by 10.223.5.76 with SMTP id 12mr3055971fau.103.1316699214214; Thu, 22 Sep 2011 06:46:54 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.18.198 with SMTP id y6cs169001lad; Thu, 22 Sep 2011 06:46:53 -0700 (PDT) Received: by 10.213.13.8 with SMTP id z8mr802407ebz.26.1316699213097; Thu, 22 Sep 2011 06:46:53 -0700 (PDT) Received: from eu1sys200aog111.obsmtp.com (eu1sys200aog111.obsmtp.com. [207.126.144.131]) by mx.google.com with SMTP id d51si2552780eea.121.2011.09.22.06.46.47 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Sep 2011 06:46:53 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.131 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.131; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.131 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob111.postini.com ([207.126.147.11]) with SMTP ID DSNKTns8Rn9t3H03WsfAGz9B4Tg214uh0MfM@postini.com; Thu, 22 Sep 2011 13:46:52 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1E93DDE; Thu, 22 Sep 2011 13:38:14 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A8481D07; Thu, 22 Sep 2011 13:46:43 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 51CE5A8065; Thu, 22 Sep 2011 15:46:37 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Thu, 22 Sep 2011 15:46:42 +0200 From: Linus Walleij To: Cc: Lee Jones , Jonas Aaberg , Thomas Gleixner , Linus Walleij Subject: [PATCH 4/7] ARM: ux500: Move timer code to separate file Date: Thu, 22 Sep 2011 15:46:40 +0200 Message-ID: <1316699200-21359-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Jonas Aaberg Just split off the timer code to its own file so we have a more fine-grained file tree. Cc: Thomas Gleixner Signed-off-by: Jonas Aaberg Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/Makefile | 2 +- arch/arm/mach-ux500/cpu.c | 36 -------------------------- arch/arm/mach-ux500/timer.c | 58 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 37 deletions(-) create mode 100644 arch/arm/mach-ux500/timer.c diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 1694916..be915a1 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -3,7 +3,7 @@ # obj-y := clock.o cpu.o devices.o devices-common.o \ - id.o usb.o + id.o usb.o timer.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index c0e4593..797f364 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -18,7 +18,6 @@ #include #include -#include #include #include #include @@ -120,38 +119,3 @@ static int ux500_l2x0_init(void) } early_initcall(ux500_l2x0_init); #endif - -static void __init ux500_timer_init(void) -{ -#ifdef CONFIG_LOCAL_TIMERS - /* Setup the local timer base */ - if (cpu_is_u5500()) - twd_base = __io_address(U5500_TWD_BASE); - else if (cpu_is_u8500()) - twd_base = __io_address(U8500_TWD_BASE); - else - ux500_unknown_soc(); -#endif - if (cpu_is_u5500()) - mtu_base = __io_address(U5500_MTU0_BASE); - else if (cpu_is_u8500ed()) - mtu_base = __io_address(U8500_MTU0_BASE_ED); - else if (cpu_is_u8500()) - mtu_base = __io_address(U8500_MTU0_BASE); - else - ux500_unknown_soc(); - - if (cpu_is_u8500()) - clksrc_dbx500_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); - else if (cpu_is_u5500()) - clksrc_dbx500_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); - else - ux500_unknown_soc(); - - nmdk_timer_init(); - clksrc_dbx500_prcmu_init(); -} - -struct sys_timer ux500_timer = { - .init = ux500_timer_init, -}; diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c new file mode 100644 index 0000000..36a82bf --- /dev/null +++ b/arch/arm/mach-ux500/timer.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + * Author: Mattias Wallin for ST-Ericsson + */ +#include +#include + +#include + +#include + +#include +#include + +static void __init ux500_timer_init(void) +{ + if (cpu_is_u5500()) { +#ifdef CONFIG_LOCAL_TIMERS + twd_base = __io_address(U5500_TWD_BASE); +#endif + mtu_base = __io_address(U5500_MTU0_BASE); + clksrc_dbx500_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); + } else if (cpu_is_u8500()) { +#ifdef CONFIG_LOCAL_TIMERS + twd_base = __io_address(U8500_TWD_BASE); +#endif + mtu_base = __io_address(U8500_MTU0_BASE); + clksrc_dbx500_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); + } else { + ux500_unknown_soc(); + } + + /* + * Here we register the timerblocks active in the system. + * Localtimers (twd) is started when both cpu is up and running. + * MTU register a clocksource, clockevent and sched_clock. + * Since the MTU is located in the VAPE power domain + * it will be cleared in sleep which makes it unsuitable. + * We however need it as a timer tick (clockevent) + * during boot to calibrate delay until twd is started. + * RTC-RTT have problems as timer tick during boot since it is + * depending on delay which is not yet calibrated. RTC-RTT is in the + * always-on powerdomain and is used as clockevent instead of twd when + * sleeping. + * The PRCMU timer 4(3 for DB5500) register a clocksource and + * sched_clock with higher rating then MTU since is always-on. + * + */ + + nmdk_timer_init(); + clksrc_dbx500_prcmu_init(); +} + +struct sys_timer ux500_timer = { + .init = ux500_timer_init, +};