From patchwork Fri Sep 9 09:17:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Hui X-Patchwork-Id: 4002 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B637A23EF5 for ; Fri, 9 Sep 2011 09:14:30 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id AA67DA186C1 for ; Fri, 9 Sep 2011 09:14:30 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id 18so3429506fxd.11 for ; Fri, 09 Sep 2011 02:14:30 -0700 (PDT) Received: by 10.223.63.8 with SMTP id z8mr1460387fah.84.1315559670573; Fri, 09 Sep 2011 02:14:30 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs8274lab; Fri, 9 Sep 2011 02:14:30 -0700 (PDT) Received: by 10.68.28.199 with SMTP id d7mr2427525pbh.142.1315559669229; Fri, 09 Sep 2011 02:14:29 -0700 (PDT) Received: from VA3EHSOBE008.bigfish.com (va3ehsobe001.messaging.microsoft.com [216.32.180.11]) by mx.google.com with ESMTPS id 20si6340898wfn.106.2011.09.09.02.14.27 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 09 Sep 2011 02:14:28 -0700 (PDT) Received-SPF: neutral (google.com: 216.32.180.11 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) client-ip=216.32.180.11; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.180.11 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) smtp.mail=jason.hui@linaro.org Received: from mail92-va3-R.bigfish.com (10.7.14.244) by VA3EHSOBE008.bigfish.com (10.7.40.28) with Microsoft SMTP Server id 14.1.225.22; Fri, 9 Sep 2011 09:14:26 +0000 Received: from mail92-va3 (localhost.localdomain [127.0.0.1]) by mail92-va3-R.bigfish.com (Postfix) with ESMTP id 4E7FF19829F; Fri, 9 Sep 2011 09:14:26 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail92-va3 (localhost.localdomain [127.0.0.1]) by mail92-va3 (MessageSwitch) id 1315559613902018_11388; Fri, 9 Sep 2011 09:13:33 +0000 (UTC) Received: from VA3EHSMHS019.bigfish.com (unknown [10.7.14.235]) by mail92-va3.bigfish.com (Postfix) with ESMTP id 08F845101C0; Fri, 9 Sep 2011 09:12:24 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS019.bigfish.com (10.7.99.29) with Microsoft SMTP Server (TLS) id 14.1.225.22; Fri, 9 Sep 2011 09:12:19 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.323.7; Fri, 9 Sep 2011 04:12:18 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p899C97b002738; Fri, 9 Sep 2011 04:12:16 -0500 (CDT) From: Jason Liu To: CC: , , , Subject: [PATCH v4 3/3] ARM: i.MX5/mm: consolidate TZIC map code Date: Fri, 9 Sep 2011 17:17:49 +0800 Message-ID: <1315559869-24838-4-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1315559869-24838-1-git-send-email-jason.hui@linaro.org> References: <1315559869-24838-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com We can use static mapping for TZIC to get rid of the duplicated code for ioremap and the error handling of ioremap, which will made code more clean and consistent This patch also removes TZIC mapping for i.mx51 TO1 since there is no support for TO1 now since the following commit: 9ab4650 (ARM: imx: Get the silicon version from the IIM module) Signed-off-by: Jason Liu Cc: Sascha Hauer --- v4: squash patches,fix the upper-letter(hex value) in comments,fix hash value v3: remove the TZIC for i.mx51 TO1 since there is no support for TO1 now. v2: Remove the MX51_DEBUG related mapping which is conflict with TZIC. MX51_DEBUG related mapping is dead code, no-one use it. --- arch/arm/mach-mx5/mm.c | 27 ++++----------------------- arch/arm/plat-mxc/include/mach/hardware.h | 6 ++++++ arch/arm/plat-mxc/include/mach/mx51.h | 4 +--- arch/arm/plat-mxc/include/mach/mx53.h | 1 + 4 files changed, 12 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index 0002b68..80998b0 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -35,6 +35,7 @@ static struct map_desc mx50_io_desc[] __initdata = { * Define the MX51 memory map. */ static struct map_desc mx51_io_desc[] __initdata = { + imx_map_entry(MX51, TZIC, MT_DEVICE), imx_map_entry(MX51, IRAM, MT_DEVICE), imx_map_entry(MX51, AIPS1, MT_DEVICE), imx_map_entry(MX51, SPBA0, MT_DEVICE), @@ -45,6 +46,7 @@ static struct map_desc mx51_io_desc[] __initdata = { * Define the MX53 memory map. */ static struct map_desc mx53_io_desc[] __initdata = { + imx_map_entry(MX53, TZIC, MT_DEVICE), imx_map_entry(MX53, AIPS1, MT_DEVICE), imx_map_entry(MX53, SPBA0, MT_DEVICE), imx_map_entry(MX53, AIPS2, MT_DEVICE), @@ -98,33 +100,12 @@ void __init mx50_init_irq(void) void __init mx51_init_irq(void) { - unsigned long tzic_addr; - void __iomem *tzic_virt; - - if (mx51_revision() < IMX_CHIP_REVISION_2_0) - tzic_addr = MX51_TZIC_BASE_ADDR_TO1; - else - tzic_addr = MX51_TZIC_BASE_ADDR; - - tzic_virt = ioremap(tzic_addr, SZ_16K); - if (!tzic_virt) - panic("unable to map TZIC interrupt controller\n"); - - tzic_init_irq(tzic_virt); + tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); } void __init mx53_init_irq(void) { - unsigned long tzic_addr; - void __iomem *tzic_virt; - - tzic_addr = MX53_TZIC_BASE_ADDR; - - tzic_virt = ioremap(tzic_addr, SZ_16K); - if (!tzic_virt) - panic("unable to map TZIC interrupt controller\n"); - - tzic_init_irq(tzic_virt); + tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); } static struct sdma_script_start_addrs imx51_sdma_script __initdata = { diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 33728aa..264a2ee 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -81,10 +81,16 @@ * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 * mx51: + * TZIC 0xe0000000+0x004000 -> 0xf5000000+0x004000 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 + * mx53: + * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 */ #define IMX_IO_P2V(x) ( \ 0xf4000000 + \ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 652f2b0..ba88550 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -120,6 +120,7 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 +#define MX51_TZIC_SIZE SZ_16K #define MX51_IO_P2V(x) IMX_IO_P2V(x) #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) @@ -338,7 +339,4 @@ extern int mx51_revision(void); extern void mx51_display_revision(void); #endif -/* tape-out 1 defines */ -#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000 - #endif /* ifndef __MACH_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 5e3c323..fbf2610 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -9,6 +9,7 @@ /* TZIC */ #define MX53_TZIC_BASE_ADDR 0x0FFFC000 +#define MX53_TZIC_SIZE SZ_16K /* * AHCI SATA