From patchwork Thu Sep 8 20:13:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 3992 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8F1B223EF9 for ; Thu, 8 Sep 2011 20:13:26 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 82D6AA1899E for ; Thu, 8 Sep 2011 20:13:26 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id 18so2780659fxd.11 for ; Thu, 08 Sep 2011 13:13:26 -0700 (PDT) Received: by 10.223.22.16 with SMTP id l16mr109824fab.62.1315512806300; Thu, 08 Sep 2011 13:13:26 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs188670lab; Thu, 8 Sep 2011 13:13:26 -0700 (PDT) Received: by 10.204.138.69 with SMTP id z5mr852320bkt.197.1315512805789; Thu, 08 Sep 2011 13:13:25 -0700 (PDT) Received: from mail.df.lth.se (mail.df.lth.se [194.47.250.12]) by mx.google.com with ESMTPS id l2si3208902bke.76.2011.09.08.13.13.25 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 08 Sep 2011 13:13:25 -0700 (PDT) Received-SPF: pass (google.com: domain of triad@df.lth.se designates 194.47.250.12 as permitted sender) client-ip=194.47.250.12; Authentication-Results: mx.google.com; spf=pass (google.com: domain of triad@df.lth.se designates 194.47.250.12 as permitted sender) smtp.mail=triad@df.lth.se Received: from mer.df.lth.se (mer.df.lth.se [194.47.250.37]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.df.lth.se (Postfix) with ESMTPS id D6FA865D6B; Thu, 8 Sep 2011 22:13:24 +0200 (CEST) Received: from mer.df.lth.se (triad@localhost.localdomain [127.0.0.1]) by mer.df.lth.se (8.14.3/8.14.3/Debian-9.4) with ESMTP id p88KDO6H021057; Thu, 8 Sep 2011 22:13:24 +0200 Received: (from triad@localhost) by mer.df.lth.se (8.14.3/8.14.3/Submit) id p88KDOVJ021056; Thu, 8 Sep 2011 22:13:24 +0200 From: Linus Walleij To: linux-arm-kernel@lists.infradead.org Cc: Lee Jones , Linus Walleij , Russell King Subject: [PATCH 3/4 v2] mach-integrator: modernize clock event registration Date: Thu, 8 Sep 2011 22:13:22 +0200 Message-Id: <1315512802-21029-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.7.2.5 Drop mult, shift and delta calculations and let the clockevent core scale this as appropriate. Set the minimum interval to 1 rather than 15 (0xf), there is nothing in the data sheets I have indicating that 15 should be some minimum value. Cc: Russell King Acked-by: Thomas Gleixner Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Don't screw around with deleting the timer_reload, it was there for a perfectly good purpose in periodic mode. --- arch/arm/mach-integrator/integrator_ap.c | 15 +++++---------- 1 files changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index e66a8bc..0a6f397 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -398,12 +398,10 @@ static int clkevt_set_next_event(unsigned long next, struct clock_event_device * static struct clock_event_device integrator_clockevent = { .name = "timer1", - .shift = 34, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_mode = clkevt_set_mode, .set_next_event = clkevt_set_next_event, .rating = 300, - .cpumask = cpu_all_mask, }; static struct irqaction integrator_timer_irq = { @@ -415,9 +413,9 @@ static struct irqaction integrator_timer_irq = { static void integrator_clockevent_init(u32 khz) { - struct clock_event_device *evt = &integrator_clockevent; unsigned int ctrl = 0; + /* Calculate and program a divisor */ if (khz * 1000 > 0x100000 * HZ) { khz /= 256; ctrl |= TIMER_CTRL_DIV256; @@ -425,17 +423,14 @@ static void integrator_clockevent_init(u32 khz) khz /= 16; ctrl |= TIMER_CTRL_DIV16; } - timer_reload = khz * 1000 / HZ; writel(ctrl, clkevt_base + TIMER_CTRL); - evt->irq = IRQ_TIMERINT1; - evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift); - evt->max_delta_ns = clockevent_delta2ns(0xffff, evt); - evt->min_delta_ns = clockevent_delta2ns(0xf, evt); - setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); - clockevents_register_device(evt); + clockevents_config_and_register(&integrator_clockevent, + khz * 1000, + 1, + 0xffffU); } /*