From patchwork Thu Sep 8 03:27:26 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Hui X-Patchwork-Id: 3970 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 242B423EFD for ; Thu, 8 Sep 2011 03:22:01 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 12A8FA1806B for ; Thu, 8 Sep 2011 03:22:01 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id 18so1701666fxd.11 for ; Wed, 07 Sep 2011 20:22:01 -0700 (PDT) Received: by 10.223.24.21 with SMTP id t21mr332828fab.24.1315452120970; Wed, 07 Sep 2011 20:22:00 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs160443lab; Wed, 7 Sep 2011 20:22:00 -0700 (PDT) Received: by 10.224.178.141 with SMTP id bm13mr106041qab.323.1315452120038; Wed, 07 Sep 2011 20:22:00 -0700 (PDT) Received: from TX2EHSOBE006.bigfish.com (tx2ehsobe003.messaging.microsoft.com. [65.55.88.13]) by mx.google.com with ESMTPS id fb3si1518229qab.46.2011.09.07.20.21.59 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Sep 2011 20:22:00 -0700 (PDT) Received-SPF: neutral (google.com: 65.55.88.13 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) client-ip=65.55.88.13; Authentication-Results: mx.google.com; spf=neutral (google.com: 65.55.88.13 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) smtp.mail=jason.hui@linaro.org Received: from mail97-tx2-R.bigfish.com (10.9.14.246) by TX2EHSOBE006.bigfish.com (10.9.40.26) with Microsoft SMTP Server id 14.1.225.22; Thu, 8 Sep 2011 03:21:58 +0000 Received: from mail97-tx2 (localhost.localdomain [127.0.0.1]) by mail97-tx2-R.bigfish.com (Postfix) with ESMTP id 0000C5482FC; Thu, 8 Sep 2011 03:21:58 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail97-tx2 (localhost.localdomain [127.0.0.1]) by mail97-tx2 (MessageSwitch) id 1315452118617594_328; Thu, 8 Sep 2011 03:21:58 +0000 (UTC) Received: from TX2EHSMHS022.bigfish.com (unknown [10.9.14.242]) by mail97-tx2.bigfish.com (Postfix) with ESMTP id 875C9BB804C; Thu, 8 Sep 2011 03:21:58 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS022.bigfish.com (10.9.99.122) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 8 Sep 2011 03:21:58 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.7; Wed, 7 Sep 2011 22:21:57 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p883LkRP008200; Wed, 7 Sep 2011 22:21:55 -0500 (CDT) From: Jason Liu To: CC: , , , Subject: [PATCH v3 3/4] ARM: i.MX5/mm: add the TZIC mapping resource Date: Thu, 8 Sep 2011 11:27:26 +0800 Message-ID: <1315452447-20205-4-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1315452447-20205-1-git-send-email-jason.hui@linaro.org> References: <1315452447-20205-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Add the TZIC mapping size and also add missing static mapping comments for the i.mx53 part Signed-off-by: Jason Liu Cc: Sascha Hauer --- arch/arm/plat-mxc/include/mach/hardware.h | 6 ++++++ arch/arm/plat-mxc/include/mach/mx51.h | 1 + arch/arm/plat-mxc/include/mach/mx53.h | 1 + 3 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 33728aa..d1ba212 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -81,10 +81,16 @@ * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 * mx51: + * TZIC 0xe0000000+0x004000 -> 0xf5000000+0x004000 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 + * mx53: + * TZIC 0x0FFFC000+0x004000 -> 0xf4bfc000+0x004000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x53F00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x63F00000+0x100000 -> 0xf5300000+0x100000 */ #define IMX_IO_P2V(x) ( \ 0xf4000000 + \ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 652f2b0..8da9d7a 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -120,6 +120,7 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 +#define MX51_TZIC_SIZE SZ_16K #define MX51_IO_P2V(x) IMX_IO_P2V(x) #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 5e3c323..fbf2610 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -9,6 +9,7 @@ /* TZIC */ #define MX53_TZIC_BASE_ADDR 0x0FFFC000 +#define MX53_TZIC_SIZE SZ_16K /* * AHCI SATA