From patchwork Wed Sep 7 16:00:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 3965 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2DF5923FA0 for ; Wed, 7 Sep 2011 16:01:03 +0000 (UTC) Received: from mail-ey0-f170.google.com (mail-ey0-f170.google.com [209.85.215.170]) by fiordland.canonical.com (Postfix) with ESMTP id 24201A184A1 for ; Wed, 7 Sep 2011 16:01:03 +0000 (UTC) Received: by eyd10 with SMTP id 10so6257148eyd.29 for ; Wed, 07 Sep 2011 09:01:03 -0700 (PDT) Received: by 10.223.22.14 with SMTP id l14mr720745fab.100.1315411262825; Wed, 07 Sep 2011 09:01:02 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs144862lab; Wed, 7 Sep 2011 09:01:02 -0700 (PDT) Received: by 10.213.25.80 with SMTP id y16mr2078472ebb.125.1315411262286; Wed, 07 Sep 2011 09:01:02 -0700 (PDT) Received: from mail-wy0-f178.google.com (mail-wy0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id b51si816605wed.24.2011.09.07.09.01.02 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Sep 2011 09:01:02 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by wyg19 with SMTP id 19so6495966wyg.37 for ; Wed, 07 Sep 2011 09:01:02 -0700 (PDT) Received: by 10.216.229.4 with SMTP id g4mr1196055weq.58.1315411261941; Wed, 07 Sep 2011 09:01:01 -0700 (PDT) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com [217.140.96.63]) by mx.google.com with ESMTPS id m2sm944412wbp.5.2011.09.07.09.01.00 (version=SSLv3 cipher=OTHER); Wed, 07 Sep 2011 09:01:01 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Colin Cross , linux-tegra@vger.kernel.org Subject: [PATCH] ARM: tegra: Remove redundant change to the CPSR in headsmp.S Date: Wed, 7 Sep 2011 17:00:53 +0100 Message-Id: <1315411253-17559-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 At secondary_startup, the MSR CPSR_cxsf, #0xd3 is not compatible with Thumb-2 and also unmasks asynchronous aborts (CPSR.A bit forced to zero -- this is probably unintentional). Any remotely sane bootloader should be putting each secondary CPU in the appropriate state _before_ entering the kernel anyway. Otherwise, disabling interrupts on entry to the kernel isn't going to fix it. Therefore this patch just removes the MSR instruction. Signed-off-by: Dave Martin --- I make assumptions about the bootloader in this patch. If someone with Tegra knowledge can please comment and/or test, that would be much appreciated, thanks. arch/arm/mach-tegra/headsmp.S | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index b5349b2..6ec4790 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -48,7 +48,6 @@ ENTRY(v7_invalidate_l1) ENDPROC(v7_invalidate_l1) ENTRY(tegra_secondary_startup) - msr cpsr_fsxc, #0xd3 bl v7_invalidate_l1 mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15