From patchwork Wed Sep 7 08:31:00 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 3952 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CF07A23EF9 for ; Wed, 7 Sep 2011 08:31:52 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id BF5E6A1825B for ; Wed, 7 Sep 2011 08:31:52 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id 18so491648fxd.11 for ; Wed, 07 Sep 2011 01:31:52 -0700 (PDT) Received: by 10.223.88.214 with SMTP id b22mr3065637fam.5.1315384312597; Wed, 07 Sep 2011 01:31:52 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs130917lab; Wed, 7 Sep 2011 01:31:52 -0700 (PDT) Received: by 10.213.108.65 with SMTP id e1mr1125469ebp.14.1315384309653; Wed, 07 Sep 2011 01:31:49 -0700 (PDT) Received: from eu1sys200aog106.obsmtp.com (eu1sys200aog106.obsmtp.com [207.126.144.121]) by mx.google.com with SMTP id k64si534200eek.109.2011.09.07.01.31.05 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Sep 2011 01:31:49 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.121 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.121; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.121 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob106.postini.com ([207.126.147.11]) with SMTP ID DSNKTmcryGJqA/R+ScoBkEn1aDvsu+s4wRpl@postini.com; Wed, 07 Sep 2011 08:31:49 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F32962CB; Wed, 7 Sep 2011 08:31:03 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8D5D71417; Wed, 7 Sep 2011 08:31:03 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 6C69324C2F2; Wed, 7 Sep 2011 10:30:58 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 7 Sep 2011 10:31:03 +0200 From: Linus Walleij To: Cc: Lee Jones , Linus Walleij , Russell King , Thomas Gleixner Subject: [PATCH 3/4] mach-integrator: modernize clock event registration Date: Wed, 7 Sep 2011 10:31:00 +0200 Message-ID: <1315384260-27404-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij Drop the reload value for the timer - the timekeeping code will call the .set_next_event to set this anyway. Drop mult, shift and delta calculations and let the clockevent core scale this as appropriate. Set the minimum interval to 1 rather than 15 (0xf), there is nothing in the data sheets I have indicating that 15 should be some minimum value. Cc: Russell King Cc: Thomas Gleixner Signed-off-by: Linus Walleij --- arch/arm/mach-integrator/integrator_ap.c | 18 +++++------------- 1 files changed, 5 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 8516193..55d3c84 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -322,8 +322,6 @@ static void __init ap_init(void) #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE) #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE) -static unsigned long timer_reload; - static void integrator_clocksource_init(u32 khz) { void __iomem *base = (void __iomem *)TIMER2_VA_BASE; @@ -394,12 +392,10 @@ static int clkevt_set_next_event(unsigned long next, struct clock_event_device * static struct clock_event_device integrator_clockevent = { .name = "timer1", - .shift = 34, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_mode = clkevt_set_mode, .set_next_event = clkevt_set_next_event, .rating = 300, - .cpumask = cpu_all_mask, }; static struct irqaction integrator_timer_irq = { @@ -411,9 +407,9 @@ static struct irqaction integrator_timer_irq = { static void integrator_clockevent_init(u32 khz) { - struct clock_event_device *evt = &integrator_clockevent; unsigned int ctrl = 0; + /* Calculate and program a divisor */ if (khz * 1000 > 0x100000 * HZ) { khz /= 256; ctrl |= TIMER_CTRL_DIV256; @@ -421,17 +417,13 @@ static void integrator_clockevent_init(u32 khz) khz /= 16; ctrl |= TIMER_CTRL_DIV16; } - - timer_reload = khz * 1000 / HZ; writel(ctrl, clkevt_base + TIMER_CTRL); - evt->irq = IRQ_TIMERINT1; - evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift); - evt->max_delta_ns = clockevent_delta2ns(0xffff, evt); - evt->min_delta_ns = clockevent_delta2ns(0xf, evt); - setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); - clockevents_register_device(evt); + clockevents_config_and_register(&integrator_clockevent, + khz * 1000, + 1, + 0xffffU); } /*