From patchwork Tue Sep 6 05:48:26 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 3874 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5297A23E54 for ; Tue, 6 Sep 2011 05:49:14 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 4916DA188DB for ; Tue, 6 Sep 2011 05:49:14 +0000 (UTC) Received: by fxd18 with SMTP id 18so5879024fxd.11 for ; Mon, 05 Sep 2011 22:49:14 -0700 (PDT) Received: by 10.223.62.8 with SMTP id v8mr1047451fah.43.1315288086687; Mon, 05 Sep 2011 22:48:06 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs83860lab; Mon, 5 Sep 2011 22:48:06 -0700 (PDT) Received: by 10.68.42.40 with SMTP id k8mr1446201pbl.163.1315288085200; Mon, 05 Sep 2011 22:48:05 -0700 (PDT) Received: from mail-pz0-f45.google.com (mail-pz0-f45.google.com [209.85.210.45]) by mx.google.com with ESMTPS id 6si9013893pbc.42.2011.09.05.22.48.04 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Sep 2011 22:48:05 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.45 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) client-ip=209.85.210.45; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.45 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) smtp.mail=shawn.guo@linaro.org Received: by mail-pz0-f45.google.com with SMTP id 33so11281599pzk.32 for ; Mon, 05 Sep 2011 22:48:04 -0700 (PDT) Received: by 10.68.48.132 with SMTP id l4mr7416845pbn.78.1315288084211; Mon, 05 Sep 2011 22:48:04 -0700 (PDT) Received: from localhost.localdomain ([114.216.158.82]) by mx.google.com with ESMTPS id x6sm27429399pba.5.2011.09.05.22.47.58 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Sep 2011 22:48:03 -0700 (PDT) From: Shawn Guo To: Russell King Cc: linux-arm-kernel@lists.infradead.org, patches@linaro.org, Shawn Guo Subject: [PATCH v2 1/2] ARM: cache-l2x0: remove __init annotation from initialization functions Date: Tue, 6 Sep 2011 13:48:26 +0800 Message-Id: <1315288107-14689-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1315288107-14689-1-git-send-email-shawn.guo@linaro.org> References: <1315288107-14689-1-git-send-email-shawn.guo@linaro.org> If ARM core gets powered off during suspend, L2 cache controller has to be reinitialized by resume procedure. The patch removes __init annotation from a few initialization functions to make the reinitialization possible. For example, platform resume function can call l2x0_of_init() to get L2 cache back to work. Signed-off-by: Shawn Guo --- arch/arm/include/asm/hardware/cache-l2x0.h | 2 +- arch/arm/mm/cache-l2x0.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index d22765c..d270310 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -89,7 +89,7 @@ #define L2X0_ADDR_FILTER_EN 1 #ifndef __ASSEMBLY__ -extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); +extern void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask); #else diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index c035b9a..7835cb6 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -280,7 +280,7 @@ static void l2x0_disable(void) spin_unlock_irqrestore(&l2x0_lock, flags); } -void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) +void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) { __u32 aux; __u32 cache_id; @@ -356,7 +356,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) } #ifdef CONFIG_OF -static void __init l2x0_of_setup(const struct device_node *np, +static void l2x0_of_setup(const struct device_node *np, __u32 *aux_val, __u32 *aux_mask) { u32 data[2] = { 0, 0 }; @@ -390,7 +390,7 @@ static void __init l2x0_of_setup(const struct device_node *np, *aux_mask &= ~mask; } -static void __init pl310_of_setup(const struct device_node *np, +static void pl310_of_setup(const struct device_node *np, __u32 *aux_val, __u32 *aux_mask) { u32 data[3] = { 0, 0, 0 }; @@ -424,14 +424,14 @@ static void __init pl310_of_setup(const struct device_node *np, } } -static const struct of_device_id l2x0_ids[] __initconst = { +static const struct of_device_id l2x0_ids[] = { { .compatible = "arm,pl310-cache", .data = pl310_of_setup }, { .compatible = "arm,l220-cache", .data = l2x0_of_setup }, { .compatible = "arm,l210-cache", .data = l2x0_of_setup }, {} }; -int __init l2x0_of_init(__u32 aux_val, __u32 aux_mask) +int l2x0_of_init(__u32 aux_val, __u32 aux_mask) { struct device_node *np; void (*l2_setup)(const struct device_node *np,