From patchwork Sun Sep 4 09:01:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 3857 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B7C6023F9E for ; Sun, 4 Sep 2011 09:01:45 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 48B50A1804D for ; Sun, 4 Sep 2011 09:01:39 +0000 (UTC) Received: by fxd18 with SMTP id 18so4097904fxd.11 for ; Sun, 04 Sep 2011 02:01:39 -0700 (PDT) Received: by 10.223.24.21 with SMTP id t21mr75068fab.24.1315126899072; Sun, 04 Sep 2011 02:01:39 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs25858lab; Sun, 4 Sep 2011 02:01:37 -0700 (PDT) Received: by 10.14.23.201 with SMTP id v49mr767196eev.116.1315126896822; Sun, 04 Sep 2011 02:01:36 -0700 (PDT) Received: from eu1sys200aog116.obsmtp.com (eu1sys200aog116.obsmtp.com [207.126.144.141]) by mx.google.com with SMTP id m13si981225eem.166.2011.09.04.02.01.28 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 04 Sep 2011 02:01:36 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.141 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.141; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.141 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob116.postini.com ([207.126.147.11]) with SMTP ID DSNKTmM+ZVW6HmWvbWUPxUaLfBCd9j6Dv3n/@postini.com; Sun, 04 Sep 2011 09:01:36 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A93B1B9; Sun, 4 Sep 2011 09:01:21 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2B13D13E5; Sun, 4 Sep 2011 09:01:21 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 0050EA8074; Sun, 4 Sep 2011 11:01:17 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Sun, 4 Sep 2011 11:01:20 +0200 From: Linus Walleij To: Cc: Lee Jones , Linus Walleij , Srinidhi Kasagar , Rabin Vincent , Adrian Bunk , Rob Herring , Catalin Marinas , Will Deacon Subject: [PATCH] ARM: l2x0: make sure I&D are not locked down on init Date: Sun, 4 Sep 2011 11:01:12 +0200 Message-ID: <1315126872-3290-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij Fighting unfixed U-Boots and other beasts that may the cache in a locked-down state when starting the kernel, we make sure to disable all cache lock-down when initializing the l2x0 so we are in a known state. Cc: Srinidhi Kasagar Cc: Rabin Vincent Cc: Adrian Bunk Cc: Rob Herring Cc: Catalin Marinas Cc: Will Deacon Reported-by: Jan Rinze Tested-by: Robert Marklund Signed-off-by: Linus Walleij --- arch/arm/mm/cache-l2x0.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 44c0867..b03c835 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -338,6 +338,10 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) writel_relaxed(1, l2x0_base + L2X0_CTRL); } + /* Make sure that I&D is not locked down when starting */ + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D); + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I); + outer_cache.inv_range = l2x0_inv_range; outer_cache.clean_range = l2x0_clean_range; outer_cache.flush_range = l2x0_flush_range;