From patchwork Wed Aug 31 02:02:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jason.chen@freescale.com X-Patchwork-Id: 3803 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3C50B23F22 for ; Wed, 31 Aug 2011 02:07:45 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 1F8F8A18506 for ; Wed, 31 Aug 2011 02:07:45 +0000 (UTC) Received: by bkbzs2 with SMTP id zs2so393417bkb.11 for ; Tue, 30 Aug 2011 19:07:45 -0700 (PDT) Received: by 10.223.62.8 with SMTP id v8mr6225537fah.43.1314756209639; Tue, 30 Aug 2011 19:03:29 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs3560lab; Tue, 30 Aug 2011 19:03:29 -0700 (PDT) Received: by 10.68.32.72 with SMTP id g8mr139133pbi.181.1314756208119; Tue, 30 Aug 2011 19:03:28 -0700 (PDT) Received: from VA3EHSOBE004.bigfish.com (va3ehsobe004.messaging.microsoft.com. [216.32.180.14]) by mx.google.com with ESMTPS id lv9si12566358pbb.61.2011.08.30.19.03.27 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 30 Aug 2011 19:03:28 -0700 (PDT) Received-SPF: neutral (google.com: 216.32.180.14 is neither permitted nor denied by best guess record for domain of B02280@freescale.com) client-ip=216.32.180.14; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.180.14 is neither permitted nor denied by best guess record for domain of B02280@freescale.com) smtp.mail=B02280@freescale.com Received: from mail185-va3-R.bigfish.com (10.7.14.253) by VA3EHSOBE004.bigfish.com (10.7.40.24) with Microsoft SMTP Server id 14.1.225.22; Wed, 31 Aug 2011 02:03:26 +0000 Received: from mail185-va3 (localhost.localdomain [127.0.0.1]) by mail185-va3-R.bigfish.com (Postfix) with ESMTP id D40D717B01F5; Wed, 31 Aug 2011 02:03:25 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bh8275dhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail185-va3 (localhost.localdomain [127.0.0.1]) by mail185-va3 (MessageSwitch) id 1314756160221029_1250; Wed, 31 Aug 2011 02:02:40 +0000 (UTC) Received: from VA3EHSMHS018.bigfish.com (unknown [10.7.14.242]) by mail185-va3.bigfish.com (Postfix) with ESMTP id 81508187826B; Wed, 31 Aug 2011 02:02:31 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS018.bigfish.com (10.7.99.28) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 31 Aug 2011 02:02:27 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.2; Tue, 30 Aug 2011 21:02:27 -0500 Received: from weitway.ap.freescale.net (weitway.ap.freescale.net [10.192.242.159]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p7V22NIZ007483; Tue, 30 Aug 2011 21:02:24 -0500 (CDT) From: To: CC: , , , Jason Chen , Jason Chen Subject: [PATCH-V3 1/2] ARM imx53: add pwm devices support Date: Wed, 31 Aug 2011 10:02:12 +0800 Message-ID: <1314756133-12676-1-git-send-email-jason.chen@freescale.com> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com From: Jason Chen Signed-off-by: Jason Chen Signed-off-by: Jason Chen --- arch/arm/mach-mx5/clock-mx51-mx53.c | 2 ++ arch/arm/mach-mx5/devices-imx53.h | 4 ++++ arch/arm/plat-mxc/devices/platform-mxc_pwm.c | 9 +++++++++ arch/arm/plat-mxc/pwm.c | 3 ++- 4 files changed, 17 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index f7bf996..f5f116f 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1507,6 +1507,8 @@ static struct clk_lookup mx53_lookups[] = { _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) + _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk) + _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) }; static void clk_tree_init(void) diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h index c27fe8b..258e68f 100644 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-mx5/devices-imx53.h @@ -40,3 +40,7 @@ extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; extern const struct imx_imx_keypad_data imx53_imx_keypad_data; #define imx53_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) + +extern const struct imx_mxc_pwm_data imx53_mxc_pwm_data[] __initconst; +#define imx53_add_mxc_pwm(id) \ + imx_add_mxc_pwm(&imx53_mxc_pwm_data[id]) diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c index b0c4ae2..18cfd07 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c @@ -49,6 +49,15 @@ const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX51 */ +#ifdef CONFIG_SOC_IMX53 +const struct imx_mxc_pwm_data imx53_mxc_pwm_data[] __initconst = { +#define imx53_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX53, _id, _hwid, SZ_16K) + imx53_mxc_pwm_data_entry(0, 1), + imx53_mxc_pwm_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX53 */ + struct platform_device *__init imx_add_mxc_pwm( const struct imx_mxc_pwm_data *data) { diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index 761c3c9..5dda436 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -57,7 +57,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; - if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { + if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51() + || cpu_is_mx53()) { unsigned long long c; unsigned long period_cycles, duty_cycles, prescale; u32 cr;