From patchwork Tue Aug 30 07:40:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 3780 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0B90123FB0 for ; Tue, 30 Aug 2011 07:40:08 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 00E82A18657 for ; Tue, 30 Aug 2011 07:40:07 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id 18so7657744fxd.11 for ; Tue, 30 Aug 2011 00:40:07 -0700 (PDT) Received: by 10.223.22.16 with SMTP id l16mr854439fab.62.1314690007815; Tue, 30 Aug 2011 00:40:07 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs124440lab; Tue, 30 Aug 2011 00:40:07 -0700 (PDT) Received: by 10.42.153.10 with SMTP id k10mr617385icw.473.1314690006567; Tue, 30 Aug 2011 00:40:06 -0700 (PDT) Received: from mail-pz0-f45.google.com (mail-pz0-f45.google.com [209.85.210.45]) by mx.google.com with ESMTPS id k2si9615476pbd.5.2011.08.30.00.40.05 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 30 Aug 2011 00:40:06 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.45 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) client-ip=209.85.210.45; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.45 is neither permitted nor denied by best guess record for domain of shawn.guo@linaro.org) smtp.mail=shawn.guo@linaro.org Received: by mail-pz0-f45.google.com with SMTP id 33so13078360pzk.32 for ; Tue, 30 Aug 2011 00:40:05 -0700 (PDT) Received: by 10.142.144.13 with SMTP id r13mr1263552wfd.311.1314690005592; Tue, 30 Aug 2011 00:40:05 -0700 (PDT) Received: from localhost.localdomain ([117.82.25.167]) by mx.google.com with ESMTPS id m2sm521635pbq.12.2011.08.30.00.39.59 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 30 Aug 2011 00:40:05 -0700 (PDT) From: Shawn Guo To: Russell King Cc: linux-arm-kernel@lists.infradead.org, patches@linaro.org, Shawn Guo Subject: [PATCH 2/3] ARM: GIC: add gic_reinit() function to help ARM resume Date: Tue, 30 Aug 2011 15:40:16 +0800 Message-Id: <1314690017-17590-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314690017-17590-1-git-send-email-shawn.guo@linaro.org> References: <1314690017-17590-1-git-send-email-shawn.guo@linaro.org> If ARM core gets powered off during suspend, GIC controller has to be reinitialized by resume procedure. This patch adds a helper function for resume procedure to reinitialize GIC. Signed-off-by: Shawn Guo --- arch/arm/common/gic.c | 15 +++++++++++++-- arch/arm/include/asm/hardware/gic.h | 1 + 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 666b278..bf0f6d8 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -255,7 +255,7 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) irq_set_chained_handler(irq, gic_handle_cascade_irq); } -static void __init gic_dist_init(struct gic_chip_data *gic, +static void gic_dist_init(struct gic_chip_data *gic, unsigned int irq_start) { unsigned int gic_irqs, irq_limit, i; @@ -326,7 +326,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic, writel_relaxed(1, base + GIC_DIST_CTRL); } -static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) +static void gic_cpu_init(struct gic_chip_data *gic) { void __iomem *dist_base = gic->dist_base; void __iomem *base = gic->cpu_base; @@ -349,6 +349,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) writel_relaxed(1, base + GIC_CPU_CTRL); } +void gic_reinit(unsigned int gic_nr, unsigned int irq_start) +{ + struct gic_chip_data *gic; + + BUG_ON(gic_nr >= MAX_GIC_NR); + + gic = &gic_data[gic_nr]; + gic_dist_init(gic, irq_start); + gic_cpu_init(gic); +} + void __init gic_init(unsigned int gic_nr, unsigned int irq_start, void __iomem *dist_base, void __iomem *cpu_base) { diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 435d3f8..9338326 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -37,6 +37,7 @@ extern void __iomem *gic_cpu_base_addr; extern struct irq_chip gic_arch_extn; void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); +void gic_reinit(unsigned int gic_nr, unsigned int irq_start); void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);