From patchwork Fri Aug 26 05:35:20 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Hui X-Patchwork-Id: 3705 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 69BC223F41 for ; Fri, 26 Aug 2011 05:30:19 +0000 (UTC) Received: from mail-gw0-f52.google.com (mail-gw0-f52.google.com [74.125.83.52]) by fiordland.canonical.com (Postfix) with ESMTP id 37DEEA18103 for ; Fri, 26 Aug 2011 05:30:19 +0000 (UTC) Received: by mail-gw0-f52.google.com with SMTP id 15so3494548gwj.11 for ; Thu, 25 Aug 2011 22:30:19 -0700 (PDT) Received: by 10.150.166.7 with SMTP id o7mr1799810ybe.98.1314336618922; Thu, 25 Aug 2011 22:30:18 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.151.27.20 with SMTP id e20cs269329ybj; Thu, 25 Aug 2011 22:30:18 -0700 (PDT) Received: by 10.227.37.17 with SMTP id v17mr552945wbd.2.1314336617961; Thu, 25 Aug 2011 22:30:17 -0700 (PDT) Received: from DB3EHSOBE003.bigfish.com (db3ehsobe003.messaging.microsoft.com [213.199.154.141]) by mx.google.com with ESMTPS id 13si3364565wbw.57.2011.08.25.22.30.17 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 25 Aug 2011 22:30:17 -0700 (PDT) Received-SPF: neutral (google.com: 213.199.154.141 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) client-ip=213.199.154.141; Authentication-Results: mx.google.com; spf=neutral (google.com: 213.199.154.141 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) smtp.mail=jason.hui@linaro.org Received: from mail97-db3-R.bigfish.com (10.3.81.248) by DB3EHSOBE003.bigfish.com (10.3.84.23) with Microsoft SMTP Server id 14.1.225.22; Fri, 26 Aug 2011 05:30:16 +0000 Received: from mail97-db3 (localhost.localdomain [127.0.0.1]) by mail97-db3-R.bigfish.com (Postfix) with ESMTP id 1414D10A836C; Fri, 26 Aug 2011 05:30:17 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bh8275dhz2dh87h2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail97-db3 (localhost.localdomain [127.0.0.1]) by mail97-db3 (MessageSwitch) id 1314336616892811_1278; Fri, 26 Aug 2011 05:30:16 +0000 (UTC) Received: from DB3EHSMHS013.bigfish.com (unknown [10.3.81.244]) by mail97-db3.bigfish.com (Postfix) with ESMTP id C8FC1EF004E; Fri, 26 Aug 2011 05:30:16 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS013.bigfish.com (10.3.87.113) with Microsoft SMTP Server (TLS) id 14.1.225.22; Fri, 26 Aug 2011 05:30:16 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.2; Fri, 26 Aug 2011 00:30:11 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p7Q5U4oY001702; Fri, 26 Aug 2011 00:30:10 -0500 (CDT) From: Jason Liu To: CC: , Subject: [[PATCH v3 3/6] ARM: mx27: Print silicon revision on boot Date: Fri, 26 Aug 2011 13:35:20 +0800 Message-ID: <1314336923-25162-4-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314336923-25162-1-git-send-email-jason.hui@linaro.org> References: <1314336923-25162-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Silicon revision is useful information to have during kernel boot. Print the MX27 silicon revision. Signed-off-by: Fabio Estevam Signed-off-by: Jason Liu Cc: Sascha Hauer --- Resend: The patch based on Fabio initial patch, I did some change to use generic function for displaying silicon revision and also some naming change to avoid using the generic name --- arch/arm/mach-imx/clock-imx27.c | 2 ++ arch/arm/mach-imx/cpu-imx27.c | 28 +++++++++++++--------------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index 6912b82..e6b1beb 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -751,6 +751,8 @@ int __init mx27_clocks_init(unsigned long fref) clk_enable(&gpio_clk); clk_enable(&emi_clk); clk_enable(&iim_clk); + imx_print_silicon_rev("i.MX27", mx27_revision()); + clk_disable(&iim_clk); #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) clk_enable(&uart1_clk); diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index 3b117be..ff38e15 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c @@ -26,12 +26,12 @@ #include -static int cpu_silicon_rev = -1; -static int cpu_partnumber; +static int mx27_cpu_rev = -1; +static int mx27_cpu_partnumber; #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ -static void query_silicon_parameter(void) +static int mx27_read_cpu_rev(void) { u32 val; /* @@ -42,20 +42,18 @@ static void query_silicon_parameter(void) val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID)); + mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF); + switch (val >> 28) { case 0: - cpu_silicon_rev = IMX_CHIP_REVISION_1_0; - break; + return IMX_CHIP_REVISION_1_0; case 1: - cpu_silicon_rev = IMX_CHIP_REVISION_2_0; - break; + return IMX_CHIP_REVISION_2_0; case 2: - cpu_silicon_rev = IMX_CHIP_REVISION_2_1; - break; + return IMX_CHIP_REVISION_2_1; default: - cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN; + return IMX_CHIP_REVISION_UNKNOWN; } - cpu_partnumber = (int)((val >> 12) & 0xFFFF); } /* @@ -65,12 +63,12 @@ static void query_silicon_parameter(void) */ int mx27_revision(void) { - if (cpu_silicon_rev == -1) - query_silicon_parameter(); + if (mx27_cpu_rev == -1) + mx27_cpu_rev = mx27_read_cpu_rev(); - if (cpu_partnumber != 0x8821) + if (mx27_cpu_partnumber != 0x8821) return -EINVAL; - return cpu_silicon_rev; + return mx27_cpu_rev; } EXPORT_SYMBOL(mx27_revision);