From patchwork Wed Aug 24 05:04:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Hui X-Patchwork-Id: 3636 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8741123F22 for ; Wed, 24 Aug 2011 04:59:36 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 6EDBBA18277 for ; Wed, 24 Aug 2011 04:59:36 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id zs2so991010bkb.11 for ; Tue, 23 Aug 2011 21:59:36 -0700 (PDT) Received: by 10.204.146.140 with SMTP id h12mr1851866bkv.226.1314161976006; Tue, 23 Aug 2011 21:59:36 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.204.41.75 with SMTP id n11cs626bke; Tue, 23 Aug 2011 21:59:35 -0700 (PDT) Received: by 10.229.31.20 with SMTP id w20mr3144460qcc.208.1314161974991; Tue, 23 Aug 2011 21:59:34 -0700 (PDT) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe004.messaging.microsoft.com [216.32.181.184]) by mx.google.com with ESMTPS id o3si382208qcy.84.2011.08.23.21.59.34 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 23 Aug 2011 21:59:34 -0700 (PDT) Received-SPF: neutral (google.com: 216.32.181.184 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) client-ip=216.32.181.184; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.184 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) smtp.mail=jason.hui@linaro.org Received: from mail76-ch1-R.bigfish.com (216.32.181.170) by CH1EHSOBE004.bigfish.com (10.43.70.54) with Microsoft SMTP Server id 14.1.225.22; Wed, 24 Aug 2011 04:59:34 +0000 Received: from mail76-ch1 (localhost.localdomain [127.0.0.1]) by mail76-ch1-R.bigfish.com (Postfix) with ESMTP id 094CB15702AA; Wed, 24 Aug 2011 04:59:34 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202hzz8275bh8275dhz2dh87h2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail76-ch1 (localhost.localdomain [127.0.0.1]) by mail76-ch1 (MessageSwitch) id 1314161972667104_17080; Wed, 24 Aug 2011 04:59:32 +0000 (UTC) Received: from CH1EHSMHS007.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.245]) by mail76-ch1.bigfish.com (Postfix) with ESMTP id 9DA7A19A004F; Wed, 24 Aug 2011 04:59:32 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS007.bigfish.com (10.43.70.7) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 24 Aug 2011 04:59:30 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.323.2; Tue, 23 Aug 2011 23:59:29 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p7O4xOa9004658; Tue, 23 Aug 2011 23:59:28 -0500 (CDT) From: Jason Liu To: CC: , Subject: [[PATCH v2 2/6] ARM: mx25: Print silicon revision on boot Date: Wed, 24 Aug 2011 13:04:33 +0800 Message-ID: <1314162277-2840-3-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314162277-2840-1-git-send-email-jason.hui@linaro.org> References: <1314162277-2840-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Silicon revision is useful information to have during kernel boot. Print the MX25 silicon revision. Signed-off-by: Fabio Estevam Signed-off-by: Jason Liu Cc: Sascha Hauer --- Resend: The patch first comes from Fabio, I did some change to use the generic function for displaying silicon revision --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/clock-imx25.c | 6 +++++ arch/arm/mach-imx/cpu-imx25.c | 41 +++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mx25.h | 4 +++ 4 files changed, 52 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e9eb36d..0a5332c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o -obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o +obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c index e63e235..b0fec74c 100644 --- a/arch/arm/mach-imx/clock-imx25.c +++ b/arch/arm/mach-imx/clock-imx25.c @@ -263,6 +263,7 @@ DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(iim_clk, 0, CCM_CGCR1, 26, NULL, NULL, NULL); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -310,6 +311,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) /* i.mx25 has the i.mx35 type sdma */ _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk) + _REGISTER_CLOCK(NULL, "iim", iim_clk) }; int __init mx25_clocks_init(void) @@ -334,6 +336,10 @@ int __init mx25_clocks_init(void) /* Clock source for gpt is ahb_div */ __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64); + clk_enable(&iim_clk); + imx_print_silicon_rev("i.MX25", mx25_revision()); + clk_disable(&iim_clk); + mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); return 0; diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c new file mode 100644 index 0000000..6914bcb --- /dev/null +++ b/arch/arm/mach-imx/cpu-imx25.c @@ -0,0 +1,41 @@ +/* + * MX25 CPU type detection + * + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include + +static int mx25_cpu_rev = -1; + +static int mx25_read_cpu_rev(void) +{ + u32 rev; + + rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV)); + switch (rev) { + case 0x00: + return IMX_CHIP_REVISION_1_0; + case 0x01: + return IMX_CHIP_REVISION_1_1; + default: + return IMX_CHIP_REVISION_UNKNOWN; + } +} + +int mx25_revision(void) +{ + if (mx25_cpu_rev == -1) + mx25_cpu_rev = mx25_read_cpu_rev(); + + return mx25_cpu_rev; +} +EXPORT_SYMBOL(mx25_revision); diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 087cd7a..8dcab80 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -104,4 +104,8 @@ #define MX25_DMA_REQ_SSI1_RX0 28 #define MX25_DMA_REQ_SSI1_TX0 29 +#ifndef __ASSEMBLY__ +extern int mx25_revision(void); +#endif + #endif /* ifndef __MACH_MX25_H__ */