From patchwork Tue Aug 23 13:07:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Hui X-Patchwork-Id: 3626 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E278823FA2 for ; Tue, 23 Aug 2011 13:04:19 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id D26B4A18729 for ; Tue, 23 Aug 2011 13:04:19 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id zs2so101257bkb.11 for ; Tue, 23 Aug 2011 06:04:19 -0700 (PDT) Received: by 10.204.152.148 with SMTP id g20mr1578650bkw.382.1314104659541; Tue, 23 Aug 2011 06:04:19 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.204.41.75 with SMTP id n11cs209851bke; Tue, 23 Aug 2011 06:04:19 -0700 (PDT) Received: by 10.216.213.29 with SMTP id z29mr3235492weo.77.1314104658972; Tue, 23 Aug 2011 06:04:18 -0700 (PDT) Received: from DB3EHSOBE001.bigfish.com (db3ehsobe001.messaging.microsoft.com [213.199.154.139]) by mx.google.com with ESMTPS id z61si379735wec.145.2011.08.23.06.04.18 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 23 Aug 2011 06:04:18 -0700 (PDT) Received-SPF: neutral (google.com: 213.199.154.139 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) client-ip=213.199.154.139; Authentication-Results: mx.google.com; spf=neutral (google.com: 213.199.154.139 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) smtp.mail=jason.hui@linaro.org Received: from mail78-db3-R.bigfish.com (10.3.81.244) by DB3EHSOBE001.bigfish.com (10.3.84.21) with Microsoft SMTP Server id 14.1.225.22; Tue, 23 Aug 2011 13:04:18 +0000 Received: from mail78-db3 (localhost.localdomain [127.0.0.1]) by mail78-db3-R.bigfish.com (Postfix) with ESMTP id 4C18512B82BE; Tue, 23 Aug 2011 13:04:18 +0000 (UTC) X-SpamScore: 7 X-BigFish: VS7(z1039ozzz1202hzz8275bh8275dhz2dh87h2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail78-db3 (localhost.localdomain [127.0.0.1]) by mail78-db3 (MessageSwitch) id 1314104627180365_13152; Tue, 23 Aug 2011 13:03:47 +0000 (UTC) Received: from DB3EHSMHS008.bigfish.com (unknown [10.3.81.242]) by mail78-db3.bigfish.com (Postfix) with ESMTP id 72FB71BD81F4; Tue, 23 Aug 2011 13:02:47 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS008.bigfish.com (10.3.87.108) with Microsoft SMTP Server (TLS) id 14.1.225.22; Tue, 23 Aug 2011 13:02:46 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.323.2; Tue, 23 Aug 2011 08:02:44 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p7ND2Wd7022085; Tue, 23 Aug 2011 08:02:42 -0500 (CDT) From: Jason Liu To: CC: , Subject: [PATCH 6/6] ARM: mx5: use generic function for displaying silicon revision Date: Tue, 23 Aug 2011 21:07:44 +0800 Message-ID: <1314104864-3725-7-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314104864-3725-1-git-send-email-jason.hui@linaro.org> References: <1314104864-3725-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Update to use generic function for displaying silicon revision Signed-off-by: Jason Liu Cc: Fabio Estevam Cc: Sascha Hauer --- arch/arm/mach-mx5/clock-mx51-mx53.c | 6 +-- arch/arm/mach-mx5/cpu.c | 74 ++++++++--------------------------- 2 files changed, 19 insertions(+), 61 deletions(-) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index f7bf996..0e23e1d 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1548,9 +1548,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&main_bus_clk); clk_enable(&iim_clk); - mx51_revision(); + imx_print_silicon_rev("i.MX51", mx51_revision()); clk_disable(&iim_clk); - mx51_display_revision(); /* move usb_phy_clk to 24MHz */ clk_set_parent(&usb_phy1_clk, &osc_clk); @@ -1592,9 +1591,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&main_bus_clk); clk_enable(&iim_clk); - mx53_revision(); + imx_print_silicon_rev("i.MX53", mx53_revision()); clk_disable(&iim_clk); - mx53_display_revision(); /* Set SDHC parents to be PLL2 */ clk_set_parent(&esdhc1_clk, &pll2_sw_clk); diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 86f87da..df46967 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -18,7 +18,7 @@ #include #include -static int cpu_silicon_rev = -1; +static int mx5_cpu_rev = -1; #define IIM_SREV 0x24 #define MX50_HW_ADADIG_DIGPROG 0xB0 @@ -28,11 +28,14 @@ static int get_mx51_srev(void) void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); u32 rev = readl(iim_base + IIM_SREV) & 0xff; - if (rev == 0x0) + switch (rev) { + case 0x0: return IMX_CHIP_REVISION_2_0; - else if (rev == 0x10) + case 0x2: return IMX_CHIP_REVISION_3_0; - return 0; + default: + return IMX_CHIP_REVISION_UNKNOWN; + } } /* @@ -45,33 +48,13 @@ int mx51_revision(void) if (!cpu_is_mx51()) return -EINVAL; - if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx51_srev(); + if (mx5_cpu_rev == -1) + mx5_cpu_rev = get_mx51_srev(); - return cpu_silicon_rev; + return mx5_cpu_rev; } EXPORT_SYMBOL(mx51_revision); -void mx51_display_revision(void) -{ - int rev; - char *srev; - rev = mx51_revision(); - - switch (rev) { - case IMX_CHIP_REVISION_2_0: - srev = IMX_CHIP_REVISION_2_0_STRING; - break; - case IMX_CHIP_REVISION_3_0: - srev = IMX_CHIP_REVISION_3_0_STRING; - break; - default: - srev = IMX_CHIP_REVISION_UNKNOWN_STRING; - } - printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev); -} -EXPORT_SYMBOL(mx51_display_revision); - #ifdef CONFIG_NEON /* @@ -121,10 +104,10 @@ int mx53_revision(void) if (!cpu_is_mx53()) return -EINVAL; - if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx53_srev(); + if (mx5_cpu_rev == -1) + mx5_cpu_rev = get_mx53_srev(); - return cpu_silicon_rev; + return mx5_cpu_rev; } EXPORT_SYMBOL(mx53_revision); @@ -134,7 +117,7 @@ static int get_mx50_srev(void) u32 rev; if (!anatop) { - cpu_silicon_rev = -EINVAL; + mx5_cpu_rev = -EINVAL; return 0; } @@ -159,36 +142,13 @@ int mx50_revision(void) if (!cpu_is_mx50()) return -EINVAL; - if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx50_srev(); + if (mx5_cpu_rev == -1) + mx5_cpu_rev = get_mx50_srev(); - return cpu_silicon_rev; + return mx5_cpu_rev; } EXPORT_SYMBOL(mx50_revision); -void mx53_display_revision(void) -{ - int rev; - char *srev; - rev = mx53_revision(); - - switch (rev) { - case IMX_CHIP_REVISION_1_0: - srev = IMX_CHIP_REVISION_1_0_STRING; - break; - case IMX_CHIP_REVISION_2_0: - srev = IMX_CHIP_REVISION_2_0_STRING; - break; - case IMX_CHIP_REVISION_2_1: - srev = IMX_CHIP_REVISION_2_1_STRING; - break; - default: - srev = IMX_CHIP_REVISION_UNKNOWN_STRING; - } - printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev); -} -EXPORT_SYMBOL(mx53_display_revision); - static int __init post_cpu_init(void) { unsigned int reg;