From patchwork Tue Aug 23 11:29:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Hui X-Patchwork-Id: 3620 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2910E23E54 for ; Tue, 23 Aug 2011 11:24:49 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 0987AA186F4 for ; Tue, 23 Aug 2011 11:24:49 +0000 (UTC) Received: by bkbzs2 with SMTP id zs2so2339bkb.11 for ; Tue, 23 Aug 2011 04:24:48 -0700 (PDT) Received: by 10.204.133.17 with SMTP id d17mr1574535bkt.122.1314098688476; Tue, 23 Aug 2011 04:24:48 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.204.41.75 with SMTP id n11cs207442bke; Tue, 23 Aug 2011 04:24:47 -0700 (PDT) Received: by 10.224.176.73 with SMTP id bd9mr2296847qab.359.1314098686589; Tue, 23 Aug 2011 04:24:46 -0700 (PDT) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe002.messaging.microsoft.com. [216.32.181.182]) by mx.google.com with ESMTPS id fl6si82870qab.89.2011.08.23.04.24.46 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 23 Aug 2011 04:24:46 -0700 (PDT) Received-SPF: neutral (google.com: 216.32.181.182 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) client-ip=216.32.181.182; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.182 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) smtp.mail=jason.hui@linaro.org Received: from mail17-ch1-R.bigfish.com (216.32.181.168) by CH1EHSOBE012.bigfish.com (10.43.70.62) with Microsoft SMTP Server id 14.1.225.22; Tue, 23 Aug 2011 11:24:45 +0000 Received: from mail17-ch1 (localhost.localdomain [127.0.0.1]) by mail17-ch1-R.bigfish.com (Postfix) with ESMTP id BAEE3260237; Tue, 23 Aug 2011 11:24:44 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail17-ch1 (localhost.localdomain [127.0.0.1]) by mail17-ch1 (MessageSwitch) id 1314098684265268_31947; Tue, 23 Aug 2011 11:24:44 +0000 (UTC) Received: from CH1EHSMHS008.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.240]) by mail17-ch1.bigfish.com (Postfix) with ESMTP id 3B3FFF7004C; Tue, 23 Aug 2011 11:24:44 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS008.bigfish.com (10.43.70.8) with Microsoft SMTP Server (TLS) id 14.1.225.22; Tue, 23 Aug 2011 11:24:42 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.323.2; Tue, 23 Aug 2011 06:24:41 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p7NBOdic003300; Tue, 23 Aug 2011 06:24:40 -0500 (CDT) From: Jason Liu To: CC: , Subject: [PATCH] ARM: i.MX5/mm: use static mapping for TZIC Date: Tue, 23 Aug 2011 19:29:34 +0800 Message-ID: <1314098974-8220-1-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com We can use static mapping for TZIC to get rid of the duplicated code for ioremap and the error handling of ioremap, which will made code more clean and consistent. Signed-off-by: Jason Liu Cc: Sascha Hauer --- v2: Remove the MX51_DEBUG related mapping which is conflict with TZIC. MX51_DEBUG related mapping is dead code, no-one use it. --- arch/arm/mach-mx5/mm.c | 21 ++++----------------- arch/arm/plat-mxc/include/mach/mx51.h | 13 +------------ arch/arm/plat-mxc/include/mach/mx53.h | 1 + 3 files changed, 6 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index f8ebe37..20dce96 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -25,8 +25,8 @@ * Define the MX51 memory map. */ static struct map_desc mx51_io_desc[] __initdata = { + imx_map_entry(MX51, TZIC, MT_DEVICE), imx_map_entry(MX51, IRAM, MT_DEVICE), - imx_map_entry(MX51, DEBUG, MT_DEVICE), imx_map_entry(MX51, AIPS1, MT_DEVICE), imx_map_entry(MX51, SPBA0, MT_DEVICE), imx_map_entry(MX51, AIPS2, MT_DEVICE), @@ -36,6 +36,7 @@ static struct map_desc mx51_io_desc[] __initdata = { * Define the MX53 memory map. */ static struct map_desc mx53_io_desc[] __initdata = { + imx_map_entry(MX53, TZIC, MT_DEVICE), imx_map_entry(MX53, AIPS1, MT_DEVICE), imx_map_entry(MX53, SPBA0, MT_DEVICE), imx_map_entry(MX53, AIPS2, MT_DEVICE), @@ -100,32 +101,18 @@ void __init imx50_init_early(void) void __init mx51_init_irq(void) { unsigned long tzic_addr; - void __iomem *tzic_virt; if (mx51_revision() < IMX_CHIP_REVISION_2_0) tzic_addr = MX51_TZIC_BASE_ADDR_TO1; else tzic_addr = MX51_TZIC_BASE_ADDR; - tzic_virt = ioremap(tzic_addr, SZ_16K); - if (!tzic_virt) - panic("unable to map TZIC interrupt controller\n"); - - tzic_init_irq(tzic_virt); + tzic_init_irq(MX51_IO_ADDRESS(tzic_addr)); } void __init mx53_init_irq(void) { - unsigned long tzic_addr; - void __iomem *tzic_virt; - - tzic_addr = MX53_TZIC_BASE_ADDR; - - tzic_virt = ioremap(tzic_addr, SZ_16K); - if (!tzic_virt) - panic("unable to map TZIC interrupt controller\n"); - - tzic_init_irq(tzic_virt); + tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); } void __init mx50_init_irq(void) diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 9666e31..414b9a8 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -18,18 +18,6 @@ #define MX51_GPU_CTRL_BASE_ADDR 0x30000000 #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 -#define MX51_DEBUG_BASE_ADDR 0x60000000 -#define MX51_DEBUG_SIZE SZ_1M - -#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) -#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000) -#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000) -#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000) -#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000) -#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000) -#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000) -#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000) - /* * SPBA global module enabled #0 */ @@ -135,6 +123,7 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 +#define MX51_TZIC_SIZE SZ_16K #define MX51_IO_P2V(x) IMX_IO_P2V(x) #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 5e3c323..fbf2610 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -9,6 +9,7 @@ /* TZIC */ #define MX53_TZIC_BASE_ADDR 0x0FFFC000 +#define MX53_TZIC_SIZE SZ_16K /* * AHCI SATA