From patchwork Tue Jul 12 11:44:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 2664 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id F186323F51 for ; Tue, 12 Jul 2011 11:46:38 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id A70EDA183A4 for ; Tue, 12 Jul 2011 11:46:38 +0000 (UTC) Received: by qwb8 with SMTP id 8so3302895qwb.11 for ; Tue, 12 Jul 2011 04:46:38 -0700 (PDT) Received: by 10.229.68.200 with SMTP id w8mr4885160qci.114.1310471198046; Tue, 12 Jul 2011 04:46:38 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.217.78 with SMTP id hl14cs240029qcb; Tue, 12 Jul 2011 04:46:37 -0700 (PDT) Received: by 10.216.220.220 with SMTP id o70mr3967590wep.71.1310471115954; Tue, 12 Jul 2011 04:45:15 -0700 (PDT) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id z4si20437493weq.66.2011.07.12.04.45.15 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 12 Jul 2011 04:45:15 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by wwe6 with SMTP id 6so4561996wwe.31 for ; Tue, 12 Jul 2011 04:45:15 -0700 (PDT) Received: by 10.216.137.164 with SMTP id y36mr4120080wei.44.1310471115030; Tue, 12 Jul 2011 04:45:15 -0700 (PDT) Received: from e200948.peterhouse.linaro.org (fw-lnat.cambridge.arm.com [217.140.96.63]) by mx.google.com with ESMTPS id o19sm6416855wbh.60.2011.07.12.04.45.13 (version=SSLv3 cipher=OTHER); Tue, 12 Jul 2011 04:45:14 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Nicolas Pitre Subject: [PATCH v2] ARM: head, zImage: Always Enter the kernel in ARM state Date: Tue, 12 Jul 2011 12:44:59 +0100 Message-Id: <1310471099-28369-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 Currently, the documented kernel entry requirements are not explicit about whether the kernel should be entered in ARM or Thumb, leading to an ambiguitity about how to enter Thumb-2 kernels. As a result, the kernel is reliant on the zImage decompressor to enter the kernel proper in the correct instruction set state. This patch changes the boot entry protocol for head.S and Image to be the same as for zImage: in all cases, the kernel is now entered in ARM. Documentation/arm/Booting is updated to reflect this new policy. A different rule will be needed for Cortex-M class CPUs as and when support for those lands in mainline, since these CPUs don't support the ARM instruction set at all: a note is added to the effect that the kernel must be entered in Thumb on such systems. Signed-off-by: Dave Martin Acked-by: Nicolas Pitre --- Reposting for comments. This was posted some weeks ago, and the feedback received has been addressed. Documentation/arm/Booting | 5 +++++ arch/arm/boot/compressed/head.S | 3 ++- arch/arm/kernel/head-nommu.S | 8 ++++++++ arch/arm/kernel/head.S | 8 ++++++++ 4 files changed, 23 insertions(+), 1 deletions(-) diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting index 4e686a2..a341d87 100644 --- a/Documentation/arm/Booting +++ b/Documentation/arm/Booting @@ -164,3 +164,8 @@ In either case, the following conditions must be met: - The boot loader is expected to call the kernel image by jumping directly to the first instruction of the kernel image. + On CPUs supporting the ARM instruction set, the entry must be + made in ARM state, even for a Thumb-2 kernel. + + On CPUs supporting only the Thumb instruction set such as + Cortex-M class CPUs, the entry must be made in Thumb state. diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index f9da419..51af709 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -353,7 +353,8 @@ not_relocated: mov r0, #0 mov r0, #0 @ must be zero mov r1, r7 @ restore architecture number mov r2, r8 @ restore atags pointer - mov pc, r4 @ call kernel + ARM( mov pc, r4 ) @ call kernel + THUMB( bx r4 ) @ entry point is always ARM .align 2 .type LC0, #object diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index 6b1e0ad..d46f259 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -32,8 +32,16 @@ * numbers for r1. * */ + .arm + __HEAD ENTRY(stext) + + THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. + THUMB( bx r9 ) @ If this is a Thumb-2 kernel, + THUMB( .thumb ) @ switch to Thumb now. + THUMB(1: ) + setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode @ and irqs disabled #ifndef CONFIG_CPU_CP15 diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 278c1b0..742b610 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -71,8 +71,16 @@ * crap here - that's what the boot loader (or in extreme, well justified * circumstances, zImage) is for. */ + .arm + __HEAD ENTRY(stext) + + THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM. + THUMB( bx r9 ) @ If this is a Thumb-2 kernel, + THUMB( .thumb ) @ switch to Thumb now. + THUMB(1: ) + setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode @ and irqs disabled mrc p15, 0, r9, c0, c0 @ get processor id