From patchwork Thu Jul 7 14:27:08 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 2529 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6B9A52412F for ; Thu, 7 Jul 2011 14:28:01 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id 3B71CA184B4 for ; Thu, 7 Jul 2011 14:28:01 +0000 (UTC) Received: by mail-qw0-f52.google.com with SMTP id 8so674060qwb.11 for ; Thu, 07 Jul 2011 07:28:01 -0700 (PDT) Received: by 10.229.1.140 with SMTP id 12mr654062qcf.118.1310048880938; Thu, 07 Jul 2011 07:28:00 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.48.135 with SMTP id r7cs109479qcf; Thu, 7 Jul 2011 07:28:00 -0700 (PDT) Received: by 10.227.19.206 with SMTP id c14mr816557wbb.0.1310048880033; Thu, 07 Jul 2011 07:28:00 -0700 (PDT) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id fy2si18895969wbb.67.2011.07.07.07.27.58 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jul 2011 07:27:59 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by wwe6 with SMTP id 6so966934wwe.31 for ; Thu, 07 Jul 2011 07:27:58 -0700 (PDT) Received: by 10.227.182.129 with SMTP id cc1mr785205wbb.10.1310048878472; Thu, 07 Jul 2011 07:27:58 -0700 (PDT) Received: from e200948.peterhouse.linaro.org (fw-lnat.cambridge.arm.com [217.140.96.63]) by mx.google.com with ESMTPS id fi5sm6928907wbb.22.2011.07.07.07.27.57 (version=SSLv3 cipher=OTHER); Thu, 07 Jul 2011 07:27:57 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Will Deacon Subject: [PATCH v4 01/40] ARM: mm: proc-macros: Add generic proc/cache/tlb struct definition macros Date: Thu, 7 Jul 2011 15:27:08 +0100 Message-Id: <1310048867-14172-2-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1310048867-14172-1-git-send-email-dave.martin@linaro.org> References: <1310048867-14172-1-git-send-email-dave.martin@linaro.org> This patch adds some generic macros to reduce boilerplate when declaring certain common structures in arch/arm/mm/*.S Thanks to Russell King for outlining what the define_processor_functions macro could look like. Currently, only a few things can be overriden when invoking the macros, based on the overrides actually required by the existing CPUs. More overrides arguments can be added in the future, if needed. Signed-off-by: Dave Martin Acked-by: Nicolas Pitre --- arch/arm/mm/proc-macros.S | 63 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 63 insertions(+), 0 deletions(-) diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 34261f9..4ae9b44 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -254,3 +254,66 @@ mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line mcr p15, 0, ip, c7, c10, 4 @ data write barrier .endm + +.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0 + .type \name\()_processor_functions, #object + .align 2 +ENTRY(\name\()_processor_functions) + .word \dabort + .word \pabort + .word cpu_\name\()_proc_init + .word cpu_\name\()_proc_fin + .word cpu_\name\()_reset + .word cpu_\name\()_do_idle + .word cpu_\name\()_dcache_clean_area + .word cpu_\name\()_switch_mm + + .if \nommu + .word 0 + .else + .word cpu_\name\()_set_pte_ext + .endif + + .if \suspend + .word cpu_\name\()_suspend_size + .word cpu_\name\()_do_suspend + .word cpu_\name\()_do_resume + .else + .word 0 + .word 0 + .word 0 + .endif + + .size \name\()_processor_functions, . - \name\()_processor_functions +.endm + +.macro define_cache_functions name:req + .align 2 + .type \name\()_cache_fns, #object +ENTRY(\name\()_cache_fns) + .long \name\()_flush_icache_all + .long \name\()_flush_kern_cache_all + .long \name\()_flush_user_cache_all + .long \name\()_flush_user_cache_range + .long \name\()_coherent_kern_range + .long \name\()_coherent_user_range + .long \name\()_flush_kern_dcache_area + .long \name\()_dma_map_area + .long \name\()_dma_unmap_area + .long \name\()_dma_flush_range + .size \name\()_cache_fns, . - \name\()_cache_fns +.endm + +.macro define_tlb_functions name:req, flags_up:req, flags_smp + .type \name\()_tlb_fns, #object +ENTRY(\name\()_tlb_fns) + .long \name\()_flush_user_tlb_range + .long \name\()_flush_kern_tlb_range + .ifnb \flags_smp + ALT_SMP(.long \flags_smp ) + ALT_UP(.long \flags_up ) + .else + .long \flags_up + .endif + .size \name\()_tlb_fns, . - \name\()_tlb_fns +.endm