From patchwork Mon Jun 20 13:40:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 2087 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id DFE0223F4D for ; Mon, 20 Jun 2011 13:48:06 +0000 (UTC) Received: from mail-vw0-f52.google.com (mail-vw0-f52.google.com [209.85.212.52]) by fiordland.canonical.com (Postfix) with ESMTP id 92BF7A18335 for ; Mon, 20 Jun 2011 13:48:06 +0000 (UTC) Received: by vws16 with SMTP id 16so3510170vws.11 for ; Mon, 20 Jun 2011 06:48:06 -0700 (PDT) Received: by 10.52.168.65 with SMTP id zu1mr3041649vdb.207.1308577685933; Mon, 20 Jun 2011 06:48:05 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.52.183.130 with SMTP id em2cs5737vdc; Mon, 20 Jun 2011 06:48:05 -0700 (PDT) Received: by 10.227.132.210 with SMTP id c18mr5088729wbt.44.1308577685150; Mon, 20 Jun 2011 06:48:05 -0700 (PDT) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id ep1si9116646wbb.146.2011.06.20.06.48.04 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Jun 2011 06:48:05 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by wwe6 with SMTP id 6so1718560wwe.31 for ; Mon, 20 Jun 2011 06:48:04 -0700 (PDT) Received: by 10.227.32.73 with SMTP id b9mr4928566wbd.86.1308577241760; Mon, 20 Jun 2011 06:40:41 -0700 (PDT) Received: from e200948.peterhouse.linaro.org (fw-lnat.cambridge.arm.com [217.140.96.63]) by mx.google.com with ESMTPS id fr17sm2359178wbb.40.2011.06.20.06.40.40 (version=SSLv3 cipher=OTHER); Mon, 20 Jun 2011 06:40:41 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Nicolas Pitre Subject: [PATCH 4/4] ARM: Documentation: clarify entry requirements for ARM versus Thumb-2 Date: Mon, 20 Jun 2011 14:40:29 +0100 Message-Id: <1308577229-23681-5-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1308577229-23681-1-git-send-email-dave.martin@linaro.org> References: <1308577229-23681-1-git-send-email-dave.martin@linaro.org> Currently, the kernel entry requirements are not explicit about whether the kernel should be entered in ARM or Thumb-2. Now that the boot protocol consistently requires the kernel Image or zImage to be entered in ARM state, document this requirement explicitly. A different rule will be needed for Cortex-M class CPUs as and when support for these lands upstream, since these CPUs don't support the ARM instruction set at all: a note is added to the effect that the kernel must be entered in Thumb on such systems. Signed-off-by: Dave Martin --- Documentation/arm/Booting | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting index 4e686a2..a341d87 100644 --- a/Documentation/arm/Booting +++ b/Documentation/arm/Booting @@ -164,3 +164,8 @@ In either case, the following conditions must be met: - The boot loader is expected to call the kernel image by jumping directly to the first instruction of the kernel image. + On CPUs supporting the ARM instruction set, the entry must be + made in ARM state, even for a Thumb-2 kernel. + + On CPUs supporting only the Thumb instruction set such as + Cortex-M class CPUs, the entry must be made in Thumb state.