From patchwork Thu Jun 9 13:01:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 1790 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.45.109) by localhost6.localdomain6 with IMAP4-SSL; 10 Jun 2011 20:11:44 -0000 Delivered-To: patches@linaro.org Received: by 10.52.181.10 with SMTP id ds10cs241246vdc; Thu, 9 Jun 2011 06:01:51 -0700 (PDT) Received: by 10.227.37.14 with SMTP id v14mr805997wbd.25.1307624510521; Thu, 09 Jun 2011 06:01:50 -0700 (PDT) Received: from mail-ww0-f42.google.com (mail-ww0-f42.google.com [74.125.82.42]) by mx.google.com with ESMTPS id fl7si4035296wbb.144.2011.06.09.06.01.49 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 09 Jun 2011 06:01:50 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.42 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=74.125.82.42; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.42 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by wwk4 with SMTP id 4so4421477wwk.1 for ; Thu, 09 Jun 2011 06:01:49 -0700 (PDT) Received: by 10.227.206.84 with SMTP id ft20mr805274wbb.21.1307624509646; Thu, 09 Jun 2011 06:01:49 -0700 (PDT) Received: from e200948.peterhouse.linaro.org (fw-lnat.cambridge.arm.com [217.140.96.63]) by mx.google.com with ESMTPS id gb6sm1211694wbb.0.2011.06.09.06.01.48 (version=SSLv3 cipher=OTHER); Thu, 09 Jun 2011 06:01:49 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Nicolas Pitre Subject: [PATCH] ARM: zImage: Add build-time check for correctly-sized proc_type entries Date: Thu, 9 Jun 2011 14:01:39 +0100 Message-Id: <1307624499-9927-1-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 It is easy to mis-maintain the proc_types table such that the entries become wrongly-sized and misaligned when the kernel is built in Thumb-2. This patch adds an assembly-time check which will turn most common size/alignment mistakes in this table into build failures, to avoid having to debug the boot-time kernel hang which would happen if the resulting kernel were actually booted. Signed-off-by: Dave Martin Acked-by: Nicolas Pitre --- KernelVersion: v3.0-rc2 arch/arm/boot/compressed/head.S | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index f9da419..0aae741 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -597,6 +597,8 @@ __common_mmu_cache_on: sub pc, lr, r0, lsr #32 @ properly flush pipeline #endif +#define PROC_ENTRY_SIZE (4*5) + /* * Here follow the relocatable cache support functions for the * various processors. This is a generic hook for locating an @@ -624,7 +626,7 @@ call_cache_fn: adr r12, proc_types ARM( addeq pc, r12, r3 ) @ call cache function THUMB( addeq r12, r3 ) THUMB( moveq pc, r12 ) @ call cache function - add r12, r12, #4*5 + add r12, r12, #PROC_ENTRY_SIZE b 1b /* @@ -794,6 +796,16 @@ proc_types: .size proc_types, . - proc_types + /* + * If you get a "non-constant expression in ".if" statement" + * error from the assembler on this line, check that you have + * not accidentally written a "b" instruction where you should + * have written W(b). + */ + .if (. - proc_types) % PROC_ENTRY_SIZE != 0 + .error "The size of one or more proc_types entries is wrong." + .endif + /* * Turn off the Cache and MMU. ARMv3 does not support * reading the control register, but ARMv4 does.