From patchwork Wed Jun 8 03:16:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 1774 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:55:44 -0000 Delivered-To: patches@linaro.org Received: by 10.52.181.10 with SMTP id ds10cs146305vdc; Tue, 7 Jun 2011 20:18:50 -0700 (PDT) Received: by 10.42.130.137 with SMTP id v9mr5625334ics.169.1307503129518; Tue, 07 Jun 2011 20:18:49 -0700 (PDT) Received: from VA3EHSOBE005.bigfish.com (va3ehsobe005.messaging.microsoft.com [216.32.180.31]) by mx.google.com with ESMTPS id el7si865363icb.6.2011.06.07.20.18.47 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 07 Jun 2011 20:18:48 -0700 (PDT) Received-SPF: neutral (google.com: 216.32.180.31 is neither permitted nor denied by best guess record for domain of richard.zhu@linaro.org) client-ip=216.32.180.31; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.180.31 is neither permitted nor denied by best guess record for domain of richard.zhu@linaro.org) smtp.mail=richard.zhu@linaro.org Received: from mail85-va3-R.bigfish.com (10.7.14.240) by VA3EHSOBE005.bigfish.com (10.7.40.25) with Microsoft SMTP Server id 14.1.225.22; Wed, 8 Jun 2011 03:18:45 +0000 Received: from mail85-va3 (localhost.localdomain [127.0.0.1]) by mail85-va3-R.bigfish.com (Postfix) with ESMTP id C3025FF0114; Wed, 8 Jun 2011 03:18:45 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail85-va3 (localhost.localdomain [127.0.0.1]) by mail85-va3 (MessageSwitch) id 1307503120412165_24102; Wed, 8 Jun 2011 03:18:40 +0000 (UTC) Received: from VA3EHSMHS019.bigfish.com (unknown [10.7.14.248]) by mail85-va3.bigfish.com (Postfix) with ESMTP id 193B32C005C; Wed, 8 Jun 2011 03:18:39 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS019.bigfish.com (10.7.99.29) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 8 Jun 2011 03:18:31 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.289.8; Tue, 7 Jun 2011 22:18:31 -0500 Received: from x-VirtualBox.ap.freescale.net (x-VirtualBox.ap.freescale.net [10.192.242.64]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p583IQ5r018989; Tue, 7 Jun 2011 22:18:27 -0500 (CDT) From: Richard Zhu To: CC: , , , , , , Richard Zhu Subject: [PATCH V1] mmc: Enable the ADMA on esdhc imx driver Date: Wed, 8 Jun 2011 11:16:45 +0800 Message-ID: <1307503005-3969-1-git-send-email-richard.zhu@linaro.org> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Eanble the ADMA2 mode on freescale esdhc imx driver, tested on MX51 and MX53. Only ADMA2 mode is enabled, MX25/35 can't support the ADMA2 mode. So this patch is only used for MX51/53. The ADMA2 mode supported or not can be distinguished by the Capability Register(offset 0x40) of eSDHC module. Up to now, only MX51/MX53 set the ADMA2 supported bit(Bit20) in the Capability Register. Signed-off-by: Richard Zhu --- drivers/mmc/host/sdhci-esdhc-imx.c | 36 +++++++++++++++++++++++++++++++----- 1 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index a19967d..8015e1a 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -31,6 +31,8 @@ #define SDHCI_VENDOR_SPEC 0xC0 #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 +#define SDHCI_SPEC_INT_ADMA_ERR 0x10000000 + #define ESDHC_FLAG_GPIO_FOR_CD_WP (1 << 0) /* * The CMDTYPE of the CMD register (offset 0xE) should be set to @@ -80,6 +82,20 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) val |= SDHCI_CARD_PRESENT; } + if (unlikely(reg == SDHCI_CAPABILITIES)) { + if (val & SDHCI_CAN_DO_ADMA1) { + val &= ~SDHCI_CAN_DO_ADMA1; + val |= SDHCI_CAN_DO_ADMA2; + } + } + + if (unlikely(reg == SDHCI_INT_STATUS)) { + if (val & SDHCI_SPEC_INT_ADMA_ERR) { + val &= ~SDHCI_SPEC_INT_ADMA_ERR; + val |= SDHCI_INT_ADMA_ERROR; + } + } + return val; } @@ -105,6 +121,13 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); } + if (unlikely((reg == SDHCI_INT_ENABLE) + || (reg == SDHCI_SIGNAL_ENABLE))) { + if (val & SDHCI_INT_ADMA_ERROR) { + val &= ~SDHCI_INT_ADMA_ERROR; + val |= SDHCI_SPEC_INT_ADMA_ERR; + } + } writel(val, host->ioaddr + reg); } @@ -154,7 +177,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) { - u32 new_val; + u16 new_val; switch (reg) { case SDHCI_POWER_CONTROL: @@ -168,10 +191,12 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS); /* ensure the endianess */ new_val |= ESDHC_HOST_CONTROL_LE; - /* DMA mode bits are shifted */ - new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; + if (val & SDHCI_CTRL_DMA_MASK) + /* DMA mode bits are shifted */ + new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; esdhc_clrset_le(host, 0xffff, new_val, reg); + return; } esdhc_clrset_le(host, 0xff, val, reg); @@ -322,9 +347,10 @@ static void esdhc_pltfm_exit(struct sdhci_host *host) } struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { - .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA + .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT + | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC + | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_BROKEN_CARD_DETECTION, - /* ADMA has issues. Might be fixable */ .ops = &sdhci_esdhc_ops, .init = esdhc_pltfm_init, .exit = esdhc_pltfm_exit,