From patchwork Tue Apr 12 05:51:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 962 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:47:47 -0000 Delivered-To: patches@linaro.org Received: by 10.68.59.138 with SMTP id z10cs143093pbq; Mon, 11 Apr 2011 22:51:26 -0700 (PDT) Received: by 10.52.188.197 with SMTP id gc5mr4334194vdc.71.1302587484316; Mon, 11 Apr 2011 22:51:24 -0700 (PDT) Received: from ch1outboundpool.messaging.microsoft.com (ch1outboundpool.messaging.microsoft.com [216.32.181.186]) by mx.google.com with ESMTPS id cy19si1804162vdb.136.2011.04.11.22.51.23 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 11 Apr 2011 22:51:24 -0700 (PDT) Received-SPF: neutral (google.com: 216.32.181.186 is neither permitted nor denied by best guess record for domain of R65037@freescale.com) client-ip=216.32.181.186; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.186 is neither permitted nor denied by best guess record for domain of R65037@freescale.com) smtp.mail=R65037@freescale.com Received: from mail197-ch1-R.bigfish.com (216.32.181.174) by CH1EHSOBE015.bigfish.com (10.43.70.65) with Microsoft SMTP Server id 14.1.225.8; Tue, 12 Apr 2011 05:51:23 +0000 Received: from mail197-ch1 (localhost.localdomain [127.0.0.1]) by mail197-ch1-R.bigfish.com (Postfix) with ESMTP id 2778516800D7; Tue, 12 Apr 2011 05:51:23 +0000 (UTC) X-SpamScore: -3 X-BigFish: VS-3(zzbb2cKzz1202hzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail197-ch1 (localhost.localdomain [127.0.0.1]) by mail197-ch1 (MessageSwitch) id 1302587482921853_11254; Tue, 12 Apr 2011 05:51:22 +0000 (UTC) Received: from CH1EHSMHS020.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.243]) by mail197-ch1.bigfish.com (Postfix) with ESMTP id CCCB0B0050; Tue, 12 Apr 2011 05:51:22 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS020.bigfish.com (10.43.70.20) with Microsoft SMTP Server (TLS) id 14.1.225.8; Tue, 12 Apr 2011 05:51:22 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.270.2; Tue, 12 Apr 2011 00:51:21 -0500 Received: from x-VirtualBox.ap.freescale.net (x-VirtualBox.ap.freescale.net [10.192.242.110]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p3C5pEWb016372; Tue, 12 Apr 2011 00:51:19 -0500 (CDT) From: Richard Zhu To: CC: , , , , , , Richard Zhu Subject: [PATCH V4 2/2] MX53 Enable the AHCI SATA on MX53 LOCO Date: Tue, 12 Apr 2011 13:51:12 +0800 Message-ID: <1302587472-20435-2-git-send-email-Hong-Xing.Zhu@freescale.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1302587472-20435-1-git-send-email-Hong-Xing.Zhu@freescale.com> References: <1302587472-20435-1-git-send-email-Hong-Xing.Zhu@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Signed-off-by: Richard Zhu --- arch/arm/mach-mx5/board-mx53_loco.c | 76 +++++++++++++++++++++++++++++++++++ 1 files changed, 76 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 0a18f8d..644aaa2 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -38,6 +39,8 @@ #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) +static struct clk *sata_clk, *sata_ref_clk; + static iomux_v3_cfg_t mx53_loco_pads[] = { /* FEC */ MX53_PAD_FEC_MDC__FEC_MDC, @@ -203,6 +206,78 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { .bitrate = 100000, }; +/* HW Initialization, if return 0, initialization is successful. */ +static int mx53_loco_sata_init(struct device *dev, void __iomem *addr) +{ + u32 tmpdata; + int ret = 0; + struct clk *clk; + + sata_clk = clk_get(dev, NULL); + if (IS_ERR(sata_clk)) { + dev_err(dev, "no sata clock.\n"); + return PTR_ERR(sata_clk); + } + ret = clk_enable(sata_clk); + if (ret) { + dev_err(dev, "can't enable sata clock.\n"); + clk_put(sata_clk); + return ret; + } + + /* FSL IMX AHCI SATA uses the internal usb phy1 clk on loco */ + sata_ref_clk = clk_get(NULL, "usb_phy1"); + if (IS_ERR(sata_ref_clk)) { + dev_err(dev, "no sata ref clock.\n"); + ret = PTR_ERR(sata_ref_clk); + goto release_sata_clk; + } + ret = clk_enable(sata_ref_clk); + if (ret) { + dev_err(dev, "can't enable sata ref clock.\n"); + clk_put(sata_ref_clk); + goto release_sata_clk; + } + + /* Get the AHB clock rate, and configure the TIMER1MS reg later */ + clk = clk_get(NULL, "ahb"); + if (IS_ERR(clk)) { + dev_err(dev, "no ahb clock.\n"); + ret = PTR_ERR(clk); + goto release_sata_ref_clk; + } + tmpdata = clk_get_rate(clk) / 1000; + clk_put(clk); + + sata_init(addr, tmpdata); + + return ret; + +release_sata_ref_clk: + clk_disable(sata_ref_clk); + clk_put(sata_ref_clk); + +release_sata_clk: + clk_disable(sata_clk); + clk_put(sata_clk); + + return ret; +} + +static void mx53_loco_sata_exit(struct device *dev) +{ + clk_disable(sata_ref_clk); + clk_put(sata_ref_clk); + + clk_disable(sata_clk); + clk_put(sata_clk); +} + +static struct ahci_platform_data sata_data = { + .init = mx53_loco_sata_init, + .exit = mx53_loco_sata_exit, +}; + static void __init mx53_loco_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, @@ -215,6 +290,7 @@ static void __init mx53_loco_board_init(void) imx53_add_imx_i2c(1, &mx53_loco_i2c_data); imx53_add_sdhci_esdhc_imx(0, NULL); imx53_add_sdhci_esdhc_imx(2, NULL); + imx53_add_ahci(0, &sata_data); } static void __init mx53_loco_timer_init(void)