From patchwork Wed Mar 2 10:04:41 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 278 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:41:24 -0000 Delivered-To: patches@linaro.org Received: by 10.224.19.208 with SMTP id c16cs177857qab; Wed, 2 Mar 2011 02:08:49 -0800 (PST) Received: by 10.52.65.225 with SMTP id a1mr1771621vdt.159.1299060529529; Wed, 02 Mar 2011 02:08:49 -0800 (PST) Received: from ch1outboundpool.messaging.microsoft.com (ch1outboundpool.messaging.microsoft.com [216.32.181.184]) by mx.google.com with ESMTPS id m10si7421168vcs.86.2011.03.02.02.08.49 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 Mar 2011 02:08:49 -0800 (PST) Received-SPF: neutral (google.com: 216.32.181.184 is neither permitted nor denied by best guess record for domain of Hong-Xing.Zhu@freescale.com) client-ip=216.32.181.184; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.184 is neither permitted nor denied by best guess record for domain of Hong-Xing.Zhu@freescale.com) smtp.mail=Hong-Xing.Zhu@freescale.com Received: from mail91-ch1-R.bigfish.com (216.32.181.170) by CH1EHSOBE003.bigfish.com (10.43.70.53) with Microsoft SMTP Server id 14.1.225.8; Wed, 2 Mar 2011 10:08:48 +0000 Received: from mail91-ch1 (localhost.localdomain [127.0.0.1]) by mail91-ch1-R.bigfish.com (Postfix) with ESMTP id D5E3C1E80CB; Wed, 2 Mar 2011 10:08:48 +0000 (UTC) X-SpamScore: -2 X-BigFish: VS-2(zzbb2cKzz1202hzz8275bh1497iz2dh2a8h668h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:az33egw01.freescale.net; RD:az33egw01.freescale.net; EFVD:NLI Received: from mail91-ch1 (localhost.localdomain [127.0.0.1]) by mail91-ch1 (MessageSwitch) id 1299060528494925_11558; Wed, 2 Mar 2011 10:08:48 +0000 (UTC) Received: from CH1EHSMHS034.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.248]) by mail91-ch1.bigfish.com (Postfix) with ESMTP id 67BFB108004E; Wed, 2 Mar 2011 10:08:48 +0000 (UTC) Received: from az33egw01.freescale.net (192.88.158.102) by CH1EHSMHS034.bigfish.com (10.43.70.34) with Microsoft SMTP Server (TLS) id 14.1.225.8; Wed, 2 Mar 2011 10:08:43 +0000 Received: from az33smr02.freescale.net (az33smr02.freescale.net [10.64.34.200]) by az33egw01.freescale.net (8.14.3/8.14.3) with ESMTP id p22A8Lww025552; Wed, 2 Mar 2011 03:08:21 -0700 (MST) Received: from x-VirtualBox.ap.freescale.net (x-VirtualBox.ap.freescale.net [10.192.242.62]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p22A7nEq004032; Wed, 2 Mar 2011 04:08:17 -0600 (CST) From: Richard Zhu To: CC: , , , , , , , , , Richard Zhu Subject: [PATCH V5 4/6] mmc: sdhci-esdhc: make the writel/readl as the general APIs Date: Wed, 2 Mar 2011 18:04:41 +0800 Message-ID: <1299060283-6404-4-git-send-email-Hong-Xing.Zhu@freescale.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1299060283-6404-1-git-send-email-Hong-Xing.Zhu@freescale.com> References: <1299060283-6404-1-git-send-email-Hong-Xing.Zhu@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Add one flag to indicate the GPIO CD/WP is enabled or not on imx platforms, and reuse the writel/readl as the general APIs for imx SOCs. Signed-off-by: Richard Zhu --- drivers/mmc/host/sdhci-esdhc-imx.c | 40 ++++++++++++++++++++++++++++++----- 1 files changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 3b52485..42f5687 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,13 @@ #include "sdhci-pltfm.h" #include "sdhci-esdhc.h" +#define IMX_GPIO_CD_WP (1 << 0) + +struct pltfm_imx_data { + int flags; + u32 mod_val; +}; + static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) { void __iomem *base = host->ioaddr + (reg & ~0x3); @@ -34,10 +42,15 @@ static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, i static u32 esdhc_readl_le(struct sdhci_host *host, int reg) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct pltfm_imx_data *imx_data = + (struct pltfm_imx_data *)pltfm_host->scratchpad; + /* fake CARD_PRESENT flag on mx25/35 */ u32 val = readl(host->ioaddr + reg); - if (unlikely(reg == SDHCI_PRESENT_STATE)) { + if (unlikely((reg == SDHCI_PRESENT_STATE) + && (imx_data->flags & IMX_GPIO_CD_WP))) { struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data; @@ -55,7 +68,12 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) { - if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct pltfm_imx_data *imx_data = + (struct pltfm_imx_data *)pltfm_host->scratchpad; + + if (unlikely((reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE) + && (imx_data->flags & IMX_GPIO_CD_WP))) /* * these interrupts won't work with a custom card_detect gpio * (only applied to mx25/35) @@ -76,6 +94,8 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg) static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct pltfm_imx_data *imx_data = + (struct pltfm_imx_data *)pltfm_host->scratchpad; switch (reg) { case SDHCI_TRANSFER_MODE: @@ -83,10 +103,10 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) * Postpone this write, we must do it together with a * command write that is down below. */ - pltfm_host->scratchpad = val; + imx_data->mod_val = val; return; case SDHCI_COMMAND: - writel(val << 16 | pltfm_host->scratchpad, + writel(val << 16 | imx_data->mod_val, host->ioaddr + SDHCI_TRANSFER_MODE); return; case SDHCI_BLOCK_SIZE: @@ -146,7 +166,9 @@ static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) } static struct sdhci_ops sdhci_esdhc_ops = { + .read_l = esdhc_readl_le, .read_w = esdhc_readw_le, + .write_l = esdhc_writel_le, .write_w = esdhc_writew_le, .write_b = esdhc_writeb_le, .set_clock = esdhc_set_clock, @@ -168,6 +190,10 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data; struct clk *clk; int err; + struct pltfm_imx_data *imx_data; + + imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL); + pltfm_host->scratchpad = (u32)imx_data; clk = clk_get(mmc_dev(host->mmc), NULL); if (IS_ERR(clk)) { @@ -214,8 +240,7 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd goto no_card_detect_irq; } - sdhci_esdhc_ops.write_l = esdhc_writel_le; - sdhci_esdhc_ops.read_l = esdhc_readl_le; + imx_data->flags |= IMX_GPIO_CD_WP; /* Now we have a working card_detect again */ host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; } @@ -234,6 +259,8 @@ static void esdhc_pltfm_exit(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data; + struct pltfm_imx_data *imx_data = + (struct pltfm_imx_data *)pltfm_host->scratchpad; if (boarddata && gpio_is_valid(boarddata->wp_gpio)) gpio_free(boarddata->wp_gpio); @@ -247,6 +274,7 @@ static void esdhc_pltfm_exit(struct sdhci_host *host) clk_disable(pltfm_host->clk); clk_put(pltfm_host->clk); + kfree(imx_data); } struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {