From patchwork Thu Feb 17 12:42:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 160 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:40:27 -0000 Delivered-To: patches@linaro.org Received: by 10.146.25.23 with SMTP id 23cs47570yay; Thu, 17 Feb 2011 04:46:44 -0800 (PST) Received: by 10.227.195.79 with SMTP id eb15mr1578412wbb.192.1297946803975; Thu, 17 Feb 2011 04:46:43 -0800 (PST) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id j3si1121662wbc.47.2011.02.17.04.46.43 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 17 Feb 2011 04:46:43 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by wwf26 with SMTP id 26so2468905wwf.31 for ; Thu, 17 Feb 2011 04:46:43 -0800 (PST) Received: by 10.227.136.66 with SMTP id q2mr1657392wbt.58.1297946803422; Thu, 17 Feb 2011 04:46:43 -0800 (PST) Received: from e200948.cambridge.arm.com (host86-144-161-218.range86-144.btcentralplus.com [86.144.161.218]) by mx.google.com with ESMTPS id f27sm691137wbf.13.2011.02.17.04.46.41 (version=SSLv3 cipher=OTHER); Thu, 17 Feb 2011 04:46:43 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: Dave Martin , Tony Lindgren , Santosh Shilimkar , Jean Pihet , Kevin Hilman , linux-omap@vger.kernel.org, Nicolas Pitre , linaro-dev@lists.linaro.org, patches@linaro.org Subject: [PATCH v5 4/5] ARM: omap3: Thumb-2 compatibility for sram34xx.S Date: Thu, 17 Feb 2011 12:42:37 +0000 Message-Id: <1297946558-13436-5-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1297946558-13436-1-git-send-email-dave.martin@linaro.org> References: <1297946558-13436-1-git-send-email-dave.martin@linaro.org> * Build unconditionally as ARM for correct interoperation with OMAP firmware. * Remove deprecated PC-relative stores * Add the required ENDPROC() directive for each ENTRY(). * .align before data words Signed-off-by: Dave Martin --- arch/arm/mach-omap2/sram34xx.S | 36 ++++++++++++++++++++++++++++-------- 1 files changed, 28 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 7f893a2..fd1531c 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -34,6 +34,12 @@ #include "sdrc.h" #include "cm2xxx_3xxx.h" +/* + * This file needs be built unconditionally as ARM to interoperate correctly + * with non-Thumb-2-capable firmware. + */ + .arm + .text /* r1 parameters */ @@ -116,24 +122,36 @@ ENTRY(omap3_sram_configure_core_dpll) @ pull the extra args off the stack @ and store them in SRAM + +/* + * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour + * in Thumb-2: use a r7 as a base instead. + * Be careful not to clobber r7 when maintaing this file. + */ + THUMB( adr r7, omap3_sram_configure_core_dpll ) + .macro strtext Rt:req, label:req + ARM( str \Rt, \label ) + THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] ) + .endm + ldr r4, [sp, #52] - str r4, omap_sdrc_rfr_ctrl_0_val + strtext r4, omap_sdrc_rfr_ctrl_0_val ldr r4, [sp, #56] - str r4, omap_sdrc_actim_ctrl_a_0_val + strtext r4, omap_sdrc_actim_ctrl_a_0_val ldr r4, [sp, #60] - str r4, omap_sdrc_actim_ctrl_b_0_val + strtext r4, omap_sdrc_actim_ctrl_b_0_val ldr r4, [sp, #64] - str r4, omap_sdrc_mr_0_val + strtext r4, omap_sdrc_mr_0_val ldr r4, [sp, #68] - str r4, omap_sdrc_rfr_ctrl_1_val + strtext r4, omap_sdrc_rfr_ctrl_1_val cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0, beq skip_cs1_params @ do not use cs1 params ldr r4, [sp, #72] - str r4, omap_sdrc_actim_ctrl_a_1_val + strtext r4, omap_sdrc_actim_ctrl_a_1_val ldr r4, [sp, #76] - str r4, omap_sdrc_actim_ctrl_b_1_val + strtext r4, omap_sdrc_actim_ctrl_b_1_val ldr r4, [sp, #80] - str r4, omap_sdrc_mr_1_val + strtext r4, omap_sdrc_mr_1_val skip_cs1_params: mrc p15, 0, r8, c1, c0, 0 @ read ctrl register bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction @@ -271,6 +289,7 @@ skip_cs1_prog: ldr r12, [r11] @ posted-write barrier for SDRC bx lr + .align omap3_sdrc_power: .word OMAP34XX_SDRC_REGADDR(SDRC_POWER) omap3_cm_clksel1_pll: @@ -319,6 +338,7 @@ omap3_sdrc_dlla_ctrl: .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) core_m2_mask_val: .word 0x07FFFFFF +ENDPROC(omap3_sram_configure_core_dpll) ENTRY(omap3_sram_configure_core_dpll_sz) .word . - omap3_sram_configure_core_dpll