From patchwork Thu Feb 17 12:42:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 161 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:40:27 -0000 Delivered-To: patches@linaro.org Received: by 10.146.25.23 with SMTP id 23cs47554yay; Thu, 17 Feb 2011 04:45:57 -0800 (PST) Received: by 10.227.156.195 with SMTP id y3mr1619180wbw.174.1297946756770; Thu, 17 Feb 2011 04:45:56 -0800 (PST) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id m10si1125262wbm.16.2011.02.17.04.45.56 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 17 Feb 2011 04:45:56 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of dave.martin@linaro.org) smtp.mail=dave.martin@linaro.org Received: by wwf26 with SMTP id 26so2468161wwf.31 for ; Thu, 17 Feb 2011 04:45:56 -0800 (PST) Received: by 10.227.198.198 with SMTP id ep6mr1581974wbb.202.1297946756180; Thu, 17 Feb 2011 04:45:56 -0800 (PST) Received: from e200948.cambridge.arm.com (host86-144-161-218.range86-144.btcentralplus.com [86.144.161.218]) by mx.google.com with ESMTPS id f27sm691137wbf.13.2011.02.17.04.45.54 (version=SSLv3 cipher=OTHER); Thu, 17 Feb 2011 04:45:55 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: Dave Martin , Tony Lindgren , Santosh Shilimkar , Jean Pihet , Kevin Hilman , linux-omap@vger.kernel.org, Nicolas Pitre , linaro-dev@lists.linaro.org, patches@linaro.org Subject: [PATCH v5 3/5] ARM: omap3: Remove hand-encoded SMC instructions Date: Thu, 17 Feb 2011 12:42:36 +0000 Message-Id: <1297946558-13436-4-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1297946558-13436-1-git-send-email-dave.martin@linaro.org> References: <1297946558-13436-1-git-send-email-dave.martin@linaro.org> For various reasons, Linux now only officially supports being built with tools which are new enough to understand the SMC instruction. Replacing the hand-encoded instructions when the mnemonic also allows for correct assembly in Thumb-2 (otherwise, the result is random data in the middle of the code). The Makefile already ensures that this file is built with a high enough gcc -march= flag (armv7-a). Signed-off-by: Dave Martin Tested-by: Santosh Shilimkar Reviewed-by: Jean Pihet Tested-by: Jean Pihet --- arch/arm/mach-omap2/sleep34xx.S | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 98d8232..a05c348 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -133,7 +133,7 @@ ENTRY(save_secure_ram_context) mov r6, #0xff mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier - .word 0xE1600071 @ call SMI monitor (smi #1) + smc #1 @ call SMI monitor (smi #1) nop nop nop @@ -408,7 +408,7 @@ skipl2dis: adr r3, l2_inv_api_params @ r3 points to dummy parameters mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier - .word 0xE1600071 @ call SMI monitor (smi #1) + smc #1 @ call SMI monitor (smi #1) /* Write to Aux control register to set some bits */ mov r0, #42 @ set service ID for PPA mov r12, r0 @ copy secure Service ID in r12 @@ -419,7 +419,7 @@ skipl2dis: ldr r3, [r4, #0xBC] @ r3 points to parameters mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier - .word 0xE1600071 @ call SMI monitor (smi #1) + smc #1 @ call SMI monitor (smi #1) #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE /* Restore L2 aux control register */ @@ -434,7 +434,7 @@ skipl2dis: adds r3, r3, #8 @ r3 points to parameters mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier - .word 0xE1600071 @ call SMI monitor (smi #1) + smc #1 @ call SMI monitor (smi #1) #endif b logic_l1_restore @@ -443,18 +443,18 @@ l2_inv_api_params: l2_inv_gp: /* Execute smi to invalidate L2 cache */ mov r12, #0x1 @ set up to invalidate L2 - .word 0xE1600070 @ Call SMI monitor (smieq) + smc #0 @ Call SMI monitor (smieq) /* Write to Aux control register to set some bits */ ldr r4, scratchpad_base ldr r3, [r4,#0xBC] ldr r0, [r3,#4] mov r12, #0x3 - .word 0xE1600070 @ Call SMI monitor (smieq) + smc #0 @ Call SMI monitor (smieq) ldr r4, scratchpad_base ldr r3, [r4,#0xBC] ldr r0, [r3,#12] mov r12, #0x2 - .word 0xE1600070 @ Call SMI monitor (smieq) + smc #0 @ Call SMI monitor (smieq) logic_l1_restore: ldr r1, l2dis_3630 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630