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[209.132.180.67]) by mx.google.com with ESMTP id zm3si29021150pac.97.2014.05.21.05.47.30; Wed, 21 May 2014 05:47:30 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752509AbaEUMr3 (ORCPT + 9 others); Wed, 21 May 2014 08:47:29 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:44086 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752508AbaEUMr1 (ORCPT ); Wed, 21 May 2014 08:47:27 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N5X00G6SCV0VS80@mailout1.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 21 May 2014 21:47:24 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.51]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id FC.39.16580.C50AC735; Wed, 21 May 2014 21:47:24 +0900 (KST) X-AuditID: cbfee691-b7f2f6d0000040c4-81-537ca05c8ffe Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 1A.1A.07139.C50AC735; Wed, 21 May 2014 21:47:24 +0900 (KST) Received: from DOKGENEKIM03 ([12.36.166.133]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N5X000W6CUZ3N80@mmp1.samsung.com>; Wed, 21 May 2014 21:47:24 +0900 (KST) From: Kukjin Kim To: 'Chirantan Ekbote' , 'Sonny Rao' Cc: 'Doug Anderson' , 'Tomasz Figa' , 'David Riley' , 'Russell King' , 'Olof Johansson' , linux-arm-kernel@lists.infradead.org, 'linux-samsung-soc' References: <1400188079-21832-1-git-send-email-chirantan@chromium.org> <53752E25.9060604@gmail.com> <53753443.8010303@gmail.com> <53753C17.1090002@gmail.com> <53754CE2.3000905@gmail.com> In-reply-to: Subject: RE: [PATCH] arm: dts: exynos5: Remove multi core timer Date: Wed, 21 May 2014 21:47:20 +0900 Message-id: <033a01cf74f2$d025ce80$70716b80$@samsung.com> MIME-version: 1.0 X-Mailer: Microsoft Outlook 14.0 Thread-index: AQFNWe4+TA1MQNXEL4KV59Y8peTylALZhXo/ApWWskQBzKu2UwEvNzgeAXj0V5ABZrsOAwG+RmGhAoAKviIBmj1l9gGntPwEAYaxxaYCW8s2jJuZxJmw X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMIsWRmVeSWpSXmKPExsVy+t8zY92YBTXBBp/niVkc/tLMZPGsm8Xi 7LKDbBabHl9jtZhxfh+Txe3LvBanrn9ms3hyZiajxapdfxgdOD1amnvYPGY3XGTx2DnrLrvH gk2lHpuX1HtcOdHE6vF5k1wAexSXTUpqTmZZapG+XQJXxu5VWxkL7ohUrLiyjr2B8bZAFyMn h4SAicTco+tYIWwxiQv31rN1MXJxCAksY5T492oGE0zRvZmfWCESixgljv1azQTh/GWUWD/x JiNIFZuAhsTh98/Yuxg5OEQEwiRmHjADqWEWWMMkcXLmWajuX6wScx5eAtvHKRAssfbMD0aQ BmEBe4nPvYUgJouAqsSuTTEgFbwClhL/pn5hgbAFJX5MvgdmMwuoS0yat4gZwpaX2LzmLTPE oQoSO86+ZgRZJSLQwihxcuUDVogiEYl9L96BJSQEejkkmnY9BEuwCAhIfJt8iAVksYSArMSm A1CDJCUOrrjBMoFRYhaS3bOQ7J6FZPcsJCsWMLKsYhRNLUguKE5KLzLVK07MLS7NS9dLzs/d xAiJ8Ik7GO8fsD7EmAy0fiKzlGhyPjBB5JXEGxqbGVmYmpgaG5lbmpEmrCTOm/4oKUhIID2x JDU7NbUgtSi+qDQntfgQIxMHp1QDY5qvwMtLSx/u0r9mIlgUu1JfpfN/yz6vhFbH11evO+wT 3MMxQ/Nbf/3DAp8jBtI8HonGnO13rZtEqw9nntiVuHj1S9UZNdoslmrpH24cPHazRuP87kj2 Tft3cvC13Zn06KvE+teCGorLy/ffjeb+Lqg1f9/CfNPZPN/kOFrf1m70KEs//46vVYmlOCPR UIu5qDgRAH0b330GAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrAKsWRmVeSWpSXmKPExsVy+t9jAd2YBTXBBhdeC1gc/tLMZPGsm8Xi 7LKDbBabHl9jtZhxfh+Txe3LvBanrn9ms3hyZiajxapdfxgdOD1amnvYPGY3XGTx2DnrLrvH gk2lHpuX1HtcOdHE6vF5k1wAe1QDo01GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5 kkJeYm6qrZKLT4CuW2YO0F1KCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMI6 xozdq7YyFtwRqVhxZR17A+NtgS5GTg4JAROJezM/sULYYhIX7q1n62Lk4hASWMQocezXaiYI 5y+jxPqJNxlBqtgENCQOv3/G3sXIwSEiECYx84AZSA2zwBomiZMzz7JCNPxilZjz8BLYWE6B YIm1Z34wgjQIC9hLfO4tBDFZBFQldm2KAangFbCU+Df1CwuELSjxY/I9MJtZQF1i0rxFzBC2 vMTmNW+ZIQ5VkNhx9jUjyCoRgRZGiZMrH7BCFIlI7HvxjnECo9AsJLNmIZk1C8msWUhaFjCy rGIUTS1ILihOSs810itOzC0uzUvXS87P3cQITh/PpHcwrmqwOMQowMGoxMO7oKg6WIg1say4 MvcQowQHs5IIr/HUmmAh3pTEyqrUovz4otKc1OJDjMlAn05klhJNzgemtrySeENjEzMjSyMz CyMTc3PShJXEeQ+2WgcKCaQnlqRmp6YWpBbBbGHi4JRqYPSeWf///MLk5xwxhvOeTuPMk8jr f/z838qn1a2x0fIGcf/nzfOW79/Zqrbfc+vpTsbgHS283+SvyLewCay7ef0Iw/dN2kwph3L+ Bi2Z13NX4OC5aazLq4SnftjLUD/F7W4L1zGRouMb338SWmS3ryxr8z1+68X+PzbXzP/vedJM y/uvUc6poIlKLMUZiYZazEXFiQAENYssYwMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: kgene.kim@samsung.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 7bit Content-language: ko Chirantan Ekbote wrote: > > >>> Anyway, I'm by no means opposed to switching to arch timers. They > >>> provide a well designed, generic interface and drivers shared by > >>> multiple platforms, which means more code sharing and possibly more eyes > >>> looking at the code, which is always good. However if they don't support > >>> low power states correctly, we can't just remove MCT. > >> > >> I think low power states aren't in mainline (right?). > >> > >> One solution that might work could be to leave the device tree entry > >> alone but change the MCT init code to simply act as a no-op if it sees > >> an arch timer is in the device tree and enabled. Then when/if someone > >> got the low power states enabled we could just change source code > >> rather than dts files. > >> > Doug and I were talking about this and we think we may have a way to > have the mct and arch timers co-exist. The main issue is that the mct > (and therefore arch timer) gets cleared once during boot and every > time we do a suspend / resume. This happens in > exynos4_mct_frc_start() but it's not immediately clear to us why the > counter needs to be reset at all. If we remove the lines that clear > the counter then there is no longer an issue with having both the mct > and the arch timers on at the same time. > Yeah, actually we don't need to reset the count value after suspend/resume. So, how about following? I think, it should be fine to you. > Alternately, if there is some code that depends on the mct being reset > we could store an offset instead of clearing the counter and then > subtract that offset every time something reads it. Doug has a patch > that does this at > https://chromium-review.googlesource.com/#/c/200298/. Effectively the > visible behavior will not change. Would either of these options work? > Hmm...I cannot open the webpage :( - Kukjin --- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 8d64200..d24db6f 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -157,12 +157,15 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo) { u32 reg; - exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); - exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); - reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); - reg |= MCT_G_TCON_START; - exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); + + if (!(reg & MCT_G_TCON_START)) { + exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); + exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); + + reg |= MCT_G_TCON_START; + exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); + } }