From patchwork Thu Jan 19 11:14:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 91860 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp224089qgi; Thu, 19 Jan 2017 03:16:41 -0800 (PST) X-Received: by 10.55.39.193 with SMTP id n184mr7253061qkn.315.1484824601239; Thu, 19 Jan 2017 03:16:41 -0800 (PST) Return-Path: Received: from bombadil.infradead.org ([65.50.211.133]) by mx.google.com with ESMTPS id p11si2394947qkh.213.2017.01.19.03.16.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jan 2017 03:16:41 -0800 (PST) Received-SPF: neutral (google.com: 65.50.211.133 is neither permitted nor denied by best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org) client-ip=65.50.211.133; Authentication-Results: mx.google.com; spf=neutral (google.com: 65.50.211.133 is neither permitted nor denied by best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cUAhr-0008En-6r; Thu, 19 Jan 2017 11:16:39 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cUAhD-00075N-Dp for linux-arm-kernel@lists.infradead.org; Thu, 19 Jan 2017 11:16:04 +0000 Received: from 172.24.1.60 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.1.60]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DYD07795; Thu, 19 Jan 2017 19:14:49 +0800 (CST) Received: from localhost (10.177.23.32) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.235.1; Thu, 19 Jan 2017 19:14:40 +0800 From: Ding Tianhong To: , , , , , , , , , Subject: [PATCH v8 0/4] arm64: arch_timer: Add workaround for hisilicon-161601 erratum Date: Thu, 19 Jan 2017 19:14:30 +0800 Message-ID: <1484824474-12172-1-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.58809FAC.0318, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 0856bde3bbf7715d055288136a94ab9b X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170119_031601_535882_8B580470 X-CRM114-Status: GOOD ( 17.83 ) X-Spam-Score: -7.4 (-------) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-7.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -3.2 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ding Tianhong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Erratum Hisilicon-161601 says that the ARM generic timer counter "has the potential to contain an erroneous value when the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected. The workaround is to reread the system count registers until the value of the second read is larger than the first one by less than 32, the system counter can be guaranteed not to return wrong value twice by back-to-back read and the error value is always larger than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL. v2: Introducing a new generic erratum handling mechanism for fsl,a008585 and hisilicon,161601. Significant rework based on feedback, including seperate the fsl erratum a008585 to another patch, update the erratum name and remove unwanted code. v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585 and make the #define __fsl_a008585_read_reg to be private to the .c file instead of being globally visible. After discussion with Marc and Will, a consensus decision was made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum, and make some generic name more specific, export timer_unstable_counter_workaround for module access. Significant rework based on feedback, including fix some alignment problem, make the #define __hisi_161601_read_reg to be private to the .c file instead of being globally visible, add more accurate annotation and modify a bit of logical format to enable arch_timer_read_ool_enabled, remove the kernel commandline parameter clocksource.arm_arch_timer.hisilicon-161601. Introduce a generic aquick framework for erratum in ACPI mode. v4: rename the quirk handler parameter to make it more generic, and avoid break loop when handling the quirk becasue it need to support multi quirks handler. update some data structures for acpi mode. v5: Adapt the new kernel-parameters.txt for latest kernel version. Set the retries of reread system counter to 50, because it is possible that some interrupts may lead to more than twice read errors and break the loop, it will trigger the warning, so we set the number of retries far beyond the number of iterations the loop has been observed to take. v6: The last 2 patches in the previous version about the ACPI mode will conflict witch Fuwei's GTDT patches, so remove the ACPI part and only support the DT base code for this patch set. We have trigger a bug when select the CONFIG_FUNCTION_GRAPH_TRACER and enable function_graph to /sys/kernel/debug/tracing/current_tracer, the system will stall into an endless loop, it looks like that the ftrace_graph_caller will be related to xxx.read_cntvct_el0 and read the system counter again, so mark the xxx.read_cntvct_el0 with notrace to fix the problem. v7: Introduce a new general config symbol named CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND to enable the workaround for any chips which has similar arch timer erratum just like "fsl,erratum_a008585" and "hisilicon,erratum_161601", modify the struct arch_timer_erratum_workaround to be compatible different chip erratum more easily, and reconstruction some code base on the new config symbol and struct, thanks to Marc's suggestion. v8: The original erratum ID could not cover all modules, which only specified , so after discussion with the soc team, we decide to use the new ID "161010101" for this timer erratum which consist of and also update the hisilicon erratum official documents. Ding Tianhong (4): arm64: arch_timer: Add device tree binding for hisilicon-161010101 erratum arm64: arch_timer: Introduce a generic erratum handing mechanism for fsl-a008585 arm64: arch_timer: Work around Erratum Hisilicon-161010101 arm64: arch timer: Add timer erratum property for Hip05-d02 and Hip06-d03 Documentation/admin-guide/kernel-parameters.txt | 9 -- Documentation/arm64/silicon-errata.txt | 43 +++--- .../devicetree/bindings/arm/arch_timer.txt | 8 ++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 1 + arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 + arch/arm64/include/asm/arch_timer.h | 38 ++---- drivers/clocksource/Kconfig | 18 +++ drivers/clocksource/arm_arch_timer.c | 150 +++++++++++++++------ 8 files changed, 173 insertions(+), 95 deletions(-) -- 1.9.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel