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Wysocki" , Shameerali Kolothum Thodi , Mostafa Saleh Subject: [PATCH v3 7/9] iommu/arm-smmu-v3: Expose the arm_smmu_attach interface Date: Wed, 9 Oct 2024 13:23:13 -0300 Message-ID: <7-v3-e2e16cd7467f+2a6a1-smmuv3_nesting_jgg@nvidia.com> In-Reply-To: <0-v3-e2e16cd7467f+2a6a1-smmuv3_nesting_jgg@nvidia.com> References: X-ClientProxiedBy: BL1PR13CA0027.namprd13.prod.outlook.com (2603:10b6:208:256::32) To CH3PR12MB8659.namprd12.prod.outlook.com (2603:10b6:610:17c::13) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PR12MB8659:EE_|DS0PR12MB8768:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d113752-b73c-4cd4-f9a2-08dce87eaf4d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|1800799024|366016|921020; X-Microsoft-Antispam-Message-Info: eXe1KiZLtsvSdPU5XJqEAUaDb3KcDQIAQxsGyCOh+gZjCPkeG3QCWq1dp2SHeM8eo4sZCuNaqb6/oaiyX0DztdVMyixjJh5YdwzwEHXupCz5v+40w3rXg0a0Tzj1GbCAhd/IPqk1vvGXtCt0C7FGX4Jc2rnzID9ddnGAnPUKXzFfeEtZIRJomS8T2UlV+miFlnL487VKamXImjBUEt9xRVcvomB7oczLB+ffpAhXw0KcyQXVjnknxxVJHr/rn4+KpRx/rraZxXO0XojN1m7fEveg4cyOuPNXKQAW8oYxIsrj/7LB3uXrdxssW50BlnQHlKgUlEsTifMbMkDz+bBLHtaKT5yMGnbrceZEWpRa0PGSUA4HuewmBu4NIKHhdstLdQDFFk/LwOR0sCXUrUMoYVi5NYSXUwg7G8VKvdUOVb+/qoGn7GfpZUWMhssCVnpx+6dGZMxW9DS4dJGjE/IFyNLK1shPA3fwHgPGUQpH+HUUT2rM+RPA6L1PL74kw0njnaznsjfO6Pqo4XJ4sVxNW4BSJ0tffD4SIG82JaRX2QWqF+3AFClUYt/Coj0yLyEqiUkXGgZya6h9sFrzrrjKjztI+CitKPFeUNZ93z0hSQE4B/GKzCbXobkcp1QvQYn5xFkh6itV8Mb3B/RFhPNdSxrHHq/jpM9SQr7YHaJQAsMlXK245S2LzXOPcnn5957FM3mHxghpdhfgYkO+pUN9OpaVhs237L4ZbVE4rSoeG3kun/wbxDgCvm6temIXrrRoc/1S8iMnZTJB9qzZnar3jjmlcS/4asNR6GhV2YLU00Dxsd9VtQ65k2GNhB20rNaclGWhFC+qfzdLaHlFDzo+dv3+vbYi7ql7RqY6Ia9apqL5Aj/AuHyLAj3dJfh7H1lFXVO4Fqsll2TauQ/WW/GZ2ZHHniPgWENxzeSiwDu0SCE/izbD4zWCFuLxSWUZebyMQI32f0Gk2OXoLbc9rC9WjjK3JEe/JNUeLqc1xPgz/Pk9ZA7wiV7zOjt68zKh1BiWvzdH5pmbBJCEQgyN+ReethmwQzRPsr8IkaJ+gpoapoNyCMwRe1ogj1pKgbnbtkW05xIrYtEqcuBwQRoPkUHcQn3C0tnnmFDhE9LIQ+jot4BZh7pHFnQbft7FRM9nRcjG5o/c42DSn0A9tOcutzvz9WNDjr8KvKsDkWMlEvtTcpyZjYHJHjax675EjvasfOBneZdaMoFKi2nze2pinnekPou/Hf+gMkhH7KfUiVNSPLyEaL3xZy1bRK9JZpb65V800+jHYjXIsUdIbXFH9YHjoXbGHkMr5pxgtMMs33a80GQokAciobWKOUDRNM7XYgKs X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:CH3PR12MB8659.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(376014)(7416014)(1800799024)(366016)(921020); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jPBCbswzEzb71qftBregg+k9uYHloAu5HeACD8DUzVn8DZsVyZ3hpKdDxZtT/nVO2XrQmi/VBlbmR6IsD2mmnCK7Z56A9LQcGtJ0U7IULVwJAu6L1hhbhHz5rr/7rref8MJnrSm1NNfQSAmlJ4+U4U8DiTALjGG9NBiOwaQWwrUll0+1/0Tv3BQ3QOb/qQ+EQimZ9riO/SCrHMWT/lPR5Ijom11nNoyfv0gYDa2i7VdeYDJZOiK9ZJCSSVQHlw/DpIJJIH+gmAluuJZS+qiY5wvcsGXs08tuoP8ZnL6onV1vLLE4B0h3XZJqA47bVALe5duo6TBxZuKdwbBsdvSxT3fw5NgU7QqT2i7GZOnOT1+N+2q/8A7BVe0N7x3LSIzg+jrZkYGmvq1Wn5eO7pLb+5MT7hszUtVRs7FRy79mJLZZ5s1dK8TDEkHfSNag6AhNSMEbgf0BtXDt6mrztZTZSTCZM84Pe+EoXHPtBH4lqwDldSRdRWi10AHlNFO5ikqh+NwrYYzW9bqhEsyGlFmpEhqrlnBDXnb3DK34ahOV7UY81gvI+kQWAdsFF7MLrdznMA5VCC8FtG475cRBdGAKaEzj+k0RTzMnZYBEZjCZXCpSoV5SzOvi6oVYXHCV1tn5jsLdDim2II1jHAerIcAkmLH6TMCLwOdXvQqJLdHi2rHUoEO6egudmHDOVLG0DGSPNEEklPrZN6/4XU3dKY12GNBjCRYXFVlO7VUJbCk3nEXcRhbPTASk76HSgcCqFkwikKmgv14PKoO6NXQJeu2kMv1eDuwlKbb6J/UHVAAriYnz3SKqisEdUWxNFQS+8tTdJuWtgQY+Gsd+fIXcxoEwySJPP0vQX4vAdbcTkNsRG57iAVJzXo3PcMYbBqnIxPRC2R5Gj/26iSM7rIafpgi/QpjIov8w5DPTE3PxvLiQrHe6pK5kqPmm8T4IeltEksY2sRYoDv1Fz0/8nj4r2YAg4SwMG6iclJ3fLCGvQXVT10OVgtvKOfSZvSSkqQ3+li6HSbPcpBMQTNYRvP65Py+NEr0g6VhLYnwshfEPu5LVhLJLVw7j7GY9IH+CKFCNXs4mdujX4ikZGjAuZ2qEusmxFRTVeFFpEQut9MvPtWSSOGannauCLtclIJXTebxAoWBcmTwRTrz1pQZ7OPsSEgaxfJTp4c9BGWm4/6511NvuDWYwkHcGaEGzEiI2vIZIHTRFocuzL6EB4WSOgkwIa35wDLcp2ZCz57WThvyyEqa2x8ytcmlumvEkA7Vd/BxoLYFV4cwI1qDAIhYFOSnah1fRtivykxl7/7BbNDYiFCvSibVZhNfGjxGYqPYBfcljnEgwoD3i5RJhPrAkW4cv87zgsBpsQEiQUd6lbvwddr3LhXAEAALC5QtmdEuyeYqKjiNnMr+b5u0FpaZl7F+0hagAxPlsoUqn9LJJPtAJDBBjh82OARh0jXMlblTsmkxrEiZo1algJ/BfhvSYP+cyIf+326cwlaiZXaCsGBIGpazXTPuDLfsmHQZ0wC36N8N+1oUBTX26+jN1vd10U3vDYn6o+NXM0ei5p6/r3AWBXFwteX4= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0d113752-b73c-4cd4-f9a2-08dce87eaf4d X-MS-Exchange-CrossTenant-AuthSource: CH3PR12MB8659.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:23:18.5693 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: RV3QZpXL9qUp5ARwKdZnmDLG33bkwAT55o14qCpseXs0MgMBrjgMcqFgQ6tQ/EJf X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8768 The arm-smmuv3-iommufd.c file will need to call these functions too. Remove statics and put them in the header file. Remove the kunit visibility protections from arm_smmu_make_abort_ste() and arm_smmu_make_s2_domain_ste(). Signed-off-by: Jason Gunthorpe Reviewed-by: Kevin Tian --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 ++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 27 +++++++++++++++++---- 2 files changed, 27 insertions(+), 22 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 80847fa386fcd2..b4b03206afbf48 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1549,7 +1549,6 @@ static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid, } } -VISIBLE_IF_KUNIT void arm_smmu_make_abort_ste(struct arm_smmu_ste *target) { memset(target, 0, sizeof(*target)); @@ -1632,7 +1631,6 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_cdtable_ste); -VISIBLE_IF_KUNIT void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, @@ -2505,8 +2503,8 @@ arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) } } -static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, - const struct arm_smmu_ste *target) +void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, + const struct arm_smmu_ste *target) { int i, j; struct arm_smmu_device *smmu = master->smmu; @@ -2671,16 +2669,6 @@ static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); } -struct arm_smmu_attach_state { - /* Inputs */ - struct iommu_domain *old_domain; - struct arm_smmu_master *master; - bool cd_needs_ats; - ioasid_t ssid; - /* Resulting state */ - bool ats_enabled; -}; - /* * Start the sequence to attach a domain to a master. The sequence contains three * steps: @@ -2701,8 +2689,8 @@ struct arm_smmu_attach_state { * new_domain can be a non-paging domain. In this case ATS will not be enabled, * and invalidations won't be tracked. */ -static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, - struct iommu_domain *new_domain) +int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, + struct iommu_domain *new_domain) { struct arm_smmu_master *master = state->master; struct arm_smmu_master_domain *master_domain; @@ -2784,7 +2772,7 @@ static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, * completes synchronizing the PCI device's ATC and finishes manipulating the * smmu_domain->devices list. */ -static void arm_smmu_attach_commit(struct arm_smmu_attach_state *state) +void arm_smmu_attach_commit(struct arm_smmu_attach_state *state) { struct arm_smmu_master *master = state->master; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 66261fd5bfb2d2..c9e5290e995a64 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -830,21 +830,22 @@ struct arm_smmu_entry_writer_ops { void (*sync)(struct arm_smmu_entry_writer *writer); }; +void arm_smmu_make_abort_ste(struct arm_smmu_ste *target); +void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, + struct arm_smmu_master *master, + struct arm_smmu_domain *smmu_domain, + bool ats_enabled); + #if IS_ENABLED(CONFIG_KUNIT) void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits); void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *cur, const __le64 *target); void arm_smmu_get_cd_used(const __le64 *ent, __le64 *used_bits); -void arm_smmu_make_abort_ste(struct arm_smmu_ste *target); void arm_smmu_make_bypass_ste(struct arm_smmu_device *smmu, struct arm_smmu_ste *target); void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, bool ats_enabled, unsigned int s1dss); -void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, - struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain, - bool ats_enabled); void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, struct mm_struct *mm, u16 asid); @@ -902,6 +903,22 @@ static inline bool arm_smmu_master_canwbs(struct arm_smmu_master *master) IOMMU_FWSPEC_PCI_RC_CANWBS; } +struct arm_smmu_attach_state { + /* Inputs */ + struct iommu_domain *old_domain; + struct arm_smmu_master *master; + bool cd_needs_ats; + ioasid_t ssid; + /* Resulting state */ + bool ats_enabled; +}; + +int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, + struct iommu_domain *new_domain); +void arm_smmu_attach_commit(struct arm_smmu_attach_state *state); +void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, + const struct arm_smmu_ste *target); + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master);